*2 Job Locations: Primary- Kiryat Gat, Secondary- Givatayim*

Required Experience:

• 3+ years of chip design development
• Experience in logic design and verification
• Knowledgeable in frontend design fundamentals, flows, and tools

Required Skills:

• Quick Learner
• Strong technical skills
• Independent with good communication skills
• Strong knowledge on logic design fundamentals – a must
• Extensive knowledge in Verilog – a must
• Knowledge in verification methodologies (UVM, System Verilog) – an advantage
• Solid backend knowledge in synthesis, power, and timing analysis – an advantage
• Extensive experience with debugging methodologies and tools – an advantage

Required Education:

BSEE or MSEE in Electrical Engineering