Required Qualifications

• 10+ years of experience in digital design verification—a must.
• 3+ years of experience managing or leading verification teams.
• Proven track record of completing two or more full block/system verification cycles.
• In-depth knowledge of VLSI verification flows, concepts, methodologies and interfaces with algorithmic models and SW.
• Expertise in verification using SystemVerilog, UVM, or other industry-standard methodologies (eRM, OVM).
• Experience in block, cluster and full chip verification levels.
• Strong problem-solving skills and the ability to debug complex functionality issues.
• Excellent leadership, communication, and organizational skills to manage and inspire a team.

Preferred Qualifications

• Hands-on experience with high-speed communication protocols like Ethernet, PCIe, or SerDes.
• Proficiency in scripting languages (e.g., Python, Perl) for automation of verification processes.
• Familiarity with formal verification techniques and tools.
• Background in system-level verification or post-silicon validation.
• Experience with project planning tools and methodologies for effective team management.