Good understanding of ASIC verification concepts and techniques. Very good knowledge of Verilog/SystemVerilog and UVM.

Experience and knowledge in Verification of SoCs related to different applications. Good Knowledge in Power aware verification and Gate level verification is preferable. Should be able to understand the Full-chip Verification requirements well and good knowledge in industry standard protocols is a plus.

Will be part of a team that handles Verification for complex SoCs and close the Verification to the challenging milestones.

SoC Verification: Full-chip VR creation as per the chip requirements and UVM/OVM Test benches creation

Support in building verification infrastructure at the chip level as per the requirements

Capable of handling multiple areas of SoC Verification: RTL, Power Aware and Gate Level Verification

Working with the team and functional leads; Some interaction with cross functional groups;

Responsibilities:

• Development of testcases utilizing constrained-random stimulus, assertions, and other checkers in SV-UVM digital mixed signal flow

• Execution to plan and regression management

• Code functional coverage and support code coverage closure

• Support GLS simulations

• File and track bugs to closure in Jira

• Interact with designers/other groups throughout the phase of verification

• Document results of assigned blocks and participate in reviews

Qualification:

• Completed university degree in electronics engineering or comparable degree

• 6+ years’ experience in writing constrained random tests in SV UVM flow

• Experience working with SV RNM behavioural models

• Experience with Cadence Incisive/Xcelium metric Driven verification tools (e.g. vManager/IMC, functional and code coverage, assertions etc)

• Experience with GLS simulations from top level

• Ability to independently analyze and debug issues