Speedata is modernizing analytics infrastructure with the first purpose-built ASIC processor, the Analytics Processing Unit (APU), for analytics and AI data workloads. Delivering up to 100x faster Apache Spark performance while cutting infrastructure TCO by 90%, the APU executes analytics operations directly in silicon with seamless integration and no code changes.
We’re looking for an experienced Lead architect to join the architecture and system engineering team.
The architect will create and define SoC for a new class of SoCs, targeted for accelerating Big Data Analytics.
The architect will be responsible for the hardware specifications and flow specifications of complicated modules in the chip and in the full system solution.
The architect will work closely with the chip design, firmware and software teams.
This is a rare opportunity to influence the future of data processing architecture.
Requirements:
● BSc or higher degree in Electrical Engineering, Computer Science or Computer Engineering. Graduated with honors.
● 6+ years of experience as a system architect for large, high-end ASIC SoCs.
● Experience with multidisciplinary HW/SW systems.
● Team player with great communication skills.
Advantages
● Deep understanding of datacenter systems
● Experience with architecture of processors, accelerators, high speed PCIe
Responsibilities:
● Definition and detailed hardware specifications of subsystems in the SoC
● Breaking down the sub-system architecture into microarchitectural blocks with the related firmware, and SW components.
● Understanding the system in which the SoC is integrated to and designing the SoC to perfectly fit into the datacenter system.
