Cognichip is an AI-first company revolutionizing semiconductor design with its Artificial Chip Intelligence (ACI)® platform. ACI® is the world's first physics-informed foundation AI model tailored…
Cognichip is an AI-first company revolutionizing semiconductor design with its Artificial Chip Intelligence (ACI)® platform. ACI® is the world's first physics-informed foundation AI model tailored…
Mission: Use AI (ACI®) to radically speed and reduce effort in chip design
Total disclosed funding: $93M
Recent round: $60M Series A led by Seligman Ventures (Apr 1, 2026)
Headcount (reported): 73
Company Overview
Problem Domain
Semiconductor chip design automation and optimization using generative and physics-informed AI.
Founded
2024
Industry
DeepTech
Tech Stack
Cloudflare
CDN
Google Tag Manager
Google Fonts
SSL/HSTS
Mobile compatible
Funding Track Record
Seed- 2025-05-15
$33M
Emergence from stealth with $33M seed
Series A- 2026-04-01
$60M
Participation from Lip-Bu Tan; Umesh Padval (Seligman) and Lip-Bu Tan join board
Investor Signal
“Includes venture firms with domain-focused deep-tech investors and participation from industry executive Lip-Bu Tan”
Founders
What we do
Join the Team
Staff Chip Engineer- Agentic Workflow
On-SiteRedwood City, CA, US
On-Site • Redwood City, CA, US
We are building next-generation agentic AI systems that co-design silicon: generating RTL, creating DV environments, analyzing PPA, and executing iterative refinement loops across the full chip-design lifecycle. We are hiring a Staff-level engineer with strong chip design expertise and deep experience in software, automation, and LLM-based agent workflows.
This role is ideal for someone who wants to shape the future of AI-assisted hardware engineering from the ground up.
What You Will Do
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Build and lead multi-agent workflows using LangGraph, LangChain, AutoGen, CrewAI, and custom orchestration frameworks.
Collaborate with AI agents to generate RTL, UVM environments, specifications, constraints, and verification artifacts.
Develop backend services, REST APIs, data pipelines, vector databases, and knowledge-graph systems to support agent memory and tool routing.
Architect CI/CD pipelines and Kubernetes-based infrastructures for scalable agentic workloads.
Define agentic playbooks, guardrails, evaluator/critic agents, and automated error-correction and refinement loops.
Integrate EDA tools (simulation, lint, CDC, synthesis, STA) into agentic workflows and validate agent outputs for correctness and manufacturability.
Required Experience
Chip Design and Verification
7–12+ years of experience in digital IC/ASIC/SoC design.
Strong proficiency in SystemVerilog RTL development and UVM-based verification.
Hands-on experience with lint, CDC/RDC analysis, timing constraints, STA, reset/power architecture, and block-level integration.
Solid understanding of microarchitecture (caches, interconnects, DMA engines, pipelines, FIFOs, and common bus protocols).
Agentic AI and LLM Systems
Experience with agent frameworks such as LangChain, LangGraph, AutoGen, CrewAI.
Strong skills in prompt engineering, context engineering, retrieval pipelines (RAG), embeddings, and vector stores.
Understanding of evaluator/critic agents, iterative refinement loops, structured reasoning, and tool-aware agent design.
Ability to decompose chip-design workflows into multi-step agentic processes.
Software and Infrastructure
Strong proficiency in Python and JavaScript.
Experience with CI/CD systems, Docker/Kubernetes, and test-driven development.
Familiarity with large-scale backend development, REST APIs, distributed systems, and both SQL and NoSQL databases.
Experience building or integrating internal dashboards or tools (React or Vue.js is a plus).
Preferred Qualifications
Background in formal verification, PPA or timing signoff, or physical design flows.
Contributions to open-source AI, agentic systems, or EDA tooling.
Experience building long-context LLM workflows, document digesters, or knowledge-graph-driven applications.
Experience designing observability, debugging, or trace-analysis tools for agentic systems.
Why This Role Matters
This is a Staff-level position with significant influence over the architecture of our agentic AI platform. You will help define how future chips are specified, designed, verified, and optimized by combining deep silicon engineering knowledge with advanced AI-driven automation. This is an opportunity to lead the creation of workflows that dramatically reduce design cycle time while improving quality and reproducibility.
