Responsibilities

• Lead the architecture, transistor-level design, and development of analog and mixed-signal circuits such as PLLs, bandgaps, LDOs, ADCs, DACs, oscillators, amplifiers, regulators, and sensor interfaces.
• Own the complete design cycle: specifications → circuit design → simulation → layout guidance → post-layout verification → silicon validation.
• Perform in-depth simulation analysis including PVT corners, Monte Carlo, jitter, noise, linearity, stability, and reliability.
• Work closely with layout engineers to ensure optimum matching, routing, parasitics, area optimization, and EM/IR compliance.
• Develop behavioral and real-number models (Verilog-A/AMS, SystemVerilog) for mixed-signal verification.
• Collaborate with digital, AMS verification, system, and product engineering teams to ensure robust integration.
• Lead and participate in technical reviews, define design methodologies, and drive continuous improvement.
• Support lab bring-up, characterize silicon, debug issues, and implement design enhancements for production.
• Mentor junior engineers, providing technical direction and best practices in analog design.

Skills

• Bachelor’s or Master’s degree in Electrical/Electronics Engineering.
• 8+ years of experience in analog/mixed-signal circuit design.
• Strong expertise in designing circuits such as PLL, ADC, DAC, LDO, bandgap reference, op-amps, comparators, bias circuits, and oscillators.
• Proficiency with EDA tools: Cadence Virtuoso, Spectre, HSPICE, Eldo, or equivalent.
• Solid understanding of CMOS device physics, mismatch, noise, reliability, device modeling, and advanced process node behavior.
• Proven experience in post-layout verification, parasitic analysis, and optimization.
• Hands-on experience with lab equipment and silicon bring-up (oscilloscopes, VNAs, SMUs, spectrum analyzers, etc.).
• Strong analytical, communication, documentation, and leadership skills.

Qualifications

• Experience working in advanced nodes (28nm, 16nm, 7nm, or below).
• Knowledge of high-speed or RF-related analog IPs (CDR, SerDes front-end, VCOs).
• Familiarity with AMS verification methodologies and co-simulation environments.
• Track record of successful tape-outs and mass-production support.
• Experience guiding or leading small design teams.