Sr Staff Analog Design Engineer | Empower Semiconductor · Teeming.ai
Empower Semiconductor
Empower Semiconductor provides integrated voltage regulator technology that reduces power, size, and energy cost for modern computing systems. The company develops a patent-pending power management…
AI HPC Power SolutionsChiplet Power SolutionsHigh Bandwidth Power SolutionsHigh Power Density SolutionsIntegrated Voltage Regulators (IVRs)Kilowatt-Class Processor Power DeliveryPower IntegritySilicon CapacitorsVertical Power Deliveryempowersemi.com
Empower Semiconductor
Empower Semiconductor provides integrated voltage regulator technology that reduces power, size, and energy cost for modern computing systems. The company develops a patent-pending power management…
AI HPC Power SolutionsChiplet Power SolutionsHigh Bandwidth Power SolutionsHigh Power Density SolutionsIntegrated Voltage Regulators (IVRs)Kilowatt-Class Processor Power DeliveryPower IntegritySilicon CapacitorsVertical Power Deliveryempowersemi.com
HQMilpitas, US
Team Size69
Open Jobs8
Total Funding$215M
Latest Fundraise8 months ago
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Sr Staff Analog Design Engineer
On-SiteMünchen, DE
On-Site • München, DE
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Empower Semiconductor, based in Silicon Valley, powers the AI revolution with its FinFast™ technology by reducing the energy footprint and total cost of ownership of data centers. Its transformational integrated voltage regulators deliver on-demand scalable power with the speed, precision and signal integrity required by AI processors. Empower’s power-management architecture shrinks solution footprint, height and component count, achieving vertical power delivery with unprecedented power density and efficiency. Learn more at www.empowersemi.com and follow us on LinkedIn.
Role Overview
To expand the team in Munich we are seeking an experienced Analog Design Engineer to contribute to the development of high-performance power management ICs in advanced CMOS nodes. In this role, you will collaborate closely with a team of circuit designers to deliver high-density, ultra efficient circuit implementations that meet aggressive performance and size targets.
The ideal candidate has 10+ years of hands-on experience in analog IC design (or 5+ years’ experience in Power IC and DC/DC design), deep expertise in custom IC development flows from definition to layout and silicon evaluation, and thrives in a startup-like, high-accountability culture.
Key Responsibilities
Qualifications:
MS in Electrical Engineering with 5+ years’ experience in Power IC design or 10+ years in Analog/Mixed-Signal IC design.
Expert-level proficiency with Cadence Virtuoso and simulation tools.
Strong understanding of analog/mixed-signal design and layout techniques: CMOS process technology manufacturing, offset, noise, efficiency, current density, ESD, reliability, test & trim, thermals.
Strong sense of ownership/accountability; able to work independently and collaboratively in a team environment, including cross-site collaboration (i.e. US and other locations).
Experience with hands-on parasitic analysis, post-layout circuit simulation and parasitic optimization is required.
Lead technical feasibility of innovative architectures for IP macro-blocks within Power ICs, i.e. power-stages, gate drivers and various sub-systems (control, diagnostics, monitoring, telemetry, voltage/current/timing references, internal supplies, etc). Explore, compare and derive KPIs and achievable specs for various architectural and process technology options by means of mathematical/prediction models, circuit models, existing designs and/or lab evaluation data.
Hands-on custom design of analog/mixed-signal IP macro-blocks in planar and FinFET technologies. Lead and own design, pre- and post-layout verification (block- and top-level), spec compliance matrix, behavioral modeling, layout implementation, documentation.
Provide guidance, reviews and CAPA to IP-level floorplan and layout implementation of analog/mixed-signal blocks, with attention to matching, shielding, routing, parasitic, electromigration, DFM, area optimization, etc.
Run layout parasitic extraction and post-layout back-annotated simulations.
Interface to the IC Design Lead and development teams to enable smooth IP integration into IC top-level.
Interface with engineering teams outside analog design (i.e. passive design, package design, digital design, verification) for what matters the IP macro-blocks being responsible for.
Support lab eval team and/or take ownership of silicon lab validation of the designed IP macro-blocks as required.
Support Test Engineering and Operations teams for product characterization and qualification.
Coordinate tasks of junior colleagues or external sub-cons: distribute, monitor, review, improve quality of work.
Excellent communication skills (verbal, written) with ability to present complex technical topics using simple and effective communication when needed, as well as the ability to deep-dive into technical details if required.
Experience in lab silicon validation of IPs within PMIC / Power ICs is desirable.
