Baya Systems

Baya Systems provides chiplet-ready semiconductor technologies focused on accelerating intelligent compute. Their core offering is a unified fabric that boosts performance and scalability for System-on-Chips (SoCs) and chiplets. This data-driven, software-defined fabric offers extreme flexibility, modularity, and efficiency by separating transport from protocol layers. Key products include WeaverPro for architectural exploration and configuration, and WeaveIP, a portfolio of interconnect products supporting advanced protocols like CHI and CXL. Baya Systems targets markets such as Data Center, Infrastructure, AI Acceleration, Automotive, and IoT, aiming to reduce risk and cost in complex system development.

AI AccelerationChipletsData CenterIntelligent ComputeInterconnectSemiconductorSoCUnified Fabricbayasystems.com

Baya Systems

AI AccelerationChipletsData CenterIntelligent ComputeInterconnectSemiconductorSoCUnified Fabricbayasystems.com

HQSanta Clara, US

Team Size85

Open Jobs32

Total Funding$36M

Latest Fundraiselast year

TL;DR

What: Software-driven, chiplet-ready semiconductor fabric IP and system software for scalable AI and HPC.

Products: WeaverPro system design/exploration platform; WeaveIP fabric/IP portfolio (NoC/fabric, cache/coherency).

Funding: Series B — USD 36.5M announced Jan 23, 2025 (lead: Maverick Silicon; strategic investor: Synopsys).

Leadership: Founder & CEO Sailesh Kumar (former Intel Fellow; founder of NetSpeed Systems).

Locations: Offices in Santa Clara, CA; Austin, TX; and Bengaluru, India.

Stage / Size: Series B; reported ~85 employees.

Company Overview

Problem Domain

Chiplet interconnects, on-chip fabric and coherency, system integration for AI acceleration and high-performance computing.

Founded

2023

Industry

Technology, Information and Internet

Funding Track Record

Series B- 2025-01-23

USD 36.5M

Strategic investment from Synopsys; participation/reinvestment from Matrix Partners and Intel Capital.

Investor Signal

“Backed by venture and strategic corporate investors including Maverick Silicon (lead), Synopsys Inc. (strategic), Matrix Partners, and Intel Capital.”

Founders

What we do

TL;DR

Company Overview

Funding Track Record

Founders

What we do

Baya Systems

AI AccelerationChipletsData CenterIntelligent ComputeInterconnectSemiconductorSoCUnified Fabricbayasystems.com

Baya Systems

AI AccelerationChipletsData CenterIntelligent ComputeInterconnectSemiconductorSoCUnified Fabricbayasystems.com

HQSanta Clara, US

Team Size85

Open Jobs32

Total Funding$36M

Latest Fundraiselast year

TL;DR

What: Software-driven, chiplet-ready semiconductor fabric IP and system software for scalable AI and HPC.

Products: WeaverPro system design/exploration platform; WeaveIP fabric/IP portfolio (NoC/fabric, cache/coherency).

Funding: Series B — USD 36.5M announced Jan 23, 2025 (lead: Maverick Silicon; strategic investor: Synopsys).

Leadership: Founder & CEO Sailesh Kumar (former Intel Fellow; founder of NetSpeed Systems).

Locations: Offices in Santa Clara, CA; Austin, TX; and Bengaluru, India.

Stage / Size: Series B; reported ~85 employees.

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Company Overview

Problem Domain

Chiplet interconnects, on-chip fabric and coherency, system integration for AI acceleration and high-performance computing.

Founded

2023

Industry

Technology, Information and Internet

Funding Track Record

Series B- 2025-01-23

USD 36.5M

Strategic investment from Synopsys; participation/reinvestment from Matrix Partners and Intel Capital.

Investor Signal

“Backed by venture and strategic corporate investors including Maverick Silicon (lead), Synopsys Inc. (strategic), Matrix Partners, and Intel Capital.”

Founders

What we do

Join the Team

Sr. Microarchitect & RTL Design Engineer

On-SiteSanta Clara County, CA, US

On-Site • Santa Clara County, CA, US

Job Title: Microarchitect & RTL Design Engineer

Location: Santa Clara, CA

About the Role: We are seeking a seasoned Microarchitect and RTL Design Engineers with a strong background in microarchitecture and RTL coding. The ideal candidate will play a key role in shaping our technology portfolio, bringing expertise and creativity to our solutions

Key Responsibilities:

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BS, MS in Electrical Engineering, Computer Engineering or Computer Science
8+ years and current hands-on experience in microarchitecture and RTL development
Proficiency in Verilog, System Verilog
Familiarity with industry-standard EDA tools and methodologies
Experience with large high-speed, pipelined, stateful designs, and low power designs
In-depth understanding of on-chip interconnects and NoCs
Experience within ARM ACE/CHI or similar coherency protocols
Experience designing IP blocks for caches, cache coherency, memory subsystems, interconnects and NOCs
Familiarity with RAS designs, QoS in fabrics, PCIe/IO is a plus
Experience with modern programming languages like Python is a plus
Excellent problem-solving skills and attention to detail
Strong communication and collaboration skills