
Baya Systems provides chiplet-ready semiconductor technologies focused on accelerating intelligent compute. Their core offering is a unified fabric that boosts performance and scalability for System-on-Chips (SoCs) and chiplets. This data-driven, software-defined fabric offers extreme flexibility, modularity, and efficiency by separating transport from protocol layers. Key products include WeaverPro for architectural exploration and configuration, and WeaveIP, a portfolio of interconnect products supporting advanced protocols like CHI and CXL. Baya Systems targets markets such as Data Center, Infrastructure, AI Acceleration, Automotive, and IoT, aiming to reduce risk and cost in complex system development.

Baya Systems provides chiplet-ready semiconductor technologies focused on accelerating intelligent compute. Their core offering is a unified fabric that boosts performance and scalability for System-on-Chips (SoCs) and chiplets. This data-driven, software-defined fabric offers extreme flexibility, modularity, and efficiency by separating transport from protocol layers. Key products include WeaverPro for architectural exploration and configuration, and WeaveIP, a portfolio of interconnect products supporting advanced protocols like CHI and CXL. Baya Systems targets markets such as Data Center, Infrastructure, AI Acceleration, Automotive, and IoT, aiming to reduce risk and cost in complex system development.
What: Software-driven, chiplet-ready semiconductor fabric IP and system software for scalable AI and HPC.
Products: WeaverPro system design/exploration platform; WeaveIP fabric/IP portfolio (NoC/fabric, cache/coherency).
Funding: Series B — USD 36.5M announced Jan 23, 2025 (lead: Maverick Silicon; strategic investor: Synopsys).
Leadership: Founder & CEO Sailesh Kumar (former Intel Fellow; founder of NetSpeed Systems).
Locations: Offices in Santa Clara, CA; Austin, TX; and Bengaluru, India.
Stage / Size: Series B; reported ~85 employees.
Chiplet interconnects, on-chip fabric and coherency, system integration for AI acceleration and high-performance computing.
2023
Technology, Information and Internet
USD 36.5M
Strategic investment from Synopsys; participation/reinvestment from Matrix Partners and Intel Capital.
“Backed by venture and strategic corporate investors including Maverick Silicon (lead), Synopsys Inc. (strategic), Matrix Partners, and Intel Capital.”
| Company |
|---|
Job Title: Senior Design for Test (DFT) Engineer
Baya Systems
Santa Clara, CA
Senior level Only
THIS ROLE IS DESIGNED FOR MINIMUM 10 YEARS OF INDUSTRY EXPERIENCE
PLEASE BE ADVISED WE WONT REPOND TO UNQUALIFIED RESUMES AT THIS TIME.
NO ENTRY LEVEL OR RCG/NCG
We are seeking a highly experienced Senior Design for Test (DFT) Engineer to architect and implement a comprehensive DFT strategy for complex System-on-Chip (SoC) designs. The ideal candidate will lead the end-to-end DFT architecture for large-scale SoCs featuring multi-domain clocking, multiple power domains, embedded memory macros, and high-speed SERDES interfaces. This role requires deep expertise in scan architecture, MBIST, LBIST, boundary scan, hierarchical DFT methodologies, and test integration for advanced technology nodes.
Key Responsibilities:
DFT Architecture & Strategy
Architect and own the complete DFT strategy for complex SoCs.
Define top-level DFT specifications including Scan architecture (full-scan, hierarchical scan, compression) Test access mechanisms (TAM) IEEE 1149.x (JTAG), 1500, 1687 (IJTAG) implementation, On-chip clock controllers (OCC),
Define DFT micro-architecture for multi-clock, multi-voltage domain designs
Develop test strategies for complex clocking schemes including PLLs, clockmuxing, and gated clocks.
Scan & ATPG Implementation
Implement scan insertion (including scan compression) and DFT integration.
Drive ATPG generation, coverage closure, and pattern validation.
Debug coverage issues and perform root-cause analysis for DRC/ATP
G failures. Optimize test time, coverage, and pattern count.
Memory BIST
Architect and integrate MBIST solutions for large numbers of embedded memory macros.
Define memory repair strategies (redundancy, fuse programming)
Support silicon bring-up and yield analysis related to memory and logic test.
SERDES & High-Speed IO Test
Define DFT and production test strategies for high-speed SERDES blocks.
Support loopback test modes, PRBS generation/checking, BERT support.
Ensure testability of analog/mixed-signal interfaces where applicable.
Collaborate with PHY and AMS teams to define structural and functional test coverage.
Clocking & Power Domain Test Strategy
Develop DFT solutions for:◦ Multiple clock domains
Asynchronous clock crossings◦ Power-gated domains
Isolation and retention logic
Implement safe test modes and low-power test methodologies
Physical & Implementation Collaboration
Work closely with RTL, Physical Design, STA, and Power teams
Drive DFT-aware floorplanning and test routing strategies.
Resolve test timing issues and congestion related to scan chains and compression logic
Silicon Bring-Up & Production Support
Support first silicon bring-up and test program correlation.
Analyze silicon failures and provide DFT-related debug.
Drive yield improvement initiatives through test enhancement.
Work with ATE teams on pattern deployment and debug.
Leadership & Cross-Functional Collaboration
Mentor junior DFT engineers.
Lead DFT reviews and sign-off processes.
Collaborate across design, verification, physical, and product engineering teams.
Influence architecture decisions to improve testability early in the design cycle
Required Qualifications
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
8+ years of hands-on DFT experience in complex SoC development.
Proven experience architecting full-chip DFT for large SoCs.• Deep expertise in:◦ Scan insertion & compression
ATPG (stuck-at, transition, path delay, bridging)◦ MBIST & memory repair flows
LBIST architecture◦ JTAG / IEEE 1149.x / 1500 / 1687
Experience with multi-clock, multi-power domain DFT implementation.
Strong knowledge of SERDES test methodologies.
Proficiency in industry-standard DFT tools (e.g., Tessent, Synopsys DFTMAX/TestMAX, Cadence Modus)
Strong debugging and silicon bring-up experience.• Experience with advanced nodes (FinFET or below preferred)
rich.goldstein@bayasystems.com