Key Responsibilities

Verification Leadership

• Derive and capture verification requirements; define verification strategy/methodology considering IP status, schedules, reuse goals, and design skews/configurations.
• Create and own the verification project plan, track metrics, status, and risks for management.
• Review work products of junior engineers (test plans, test cases, testbench code, etc.); mentor a team

Testbench Architecture & Execution

• Architect testbenches based on verification/design requirements; build reusable environments for multiple configurations.
• Create test suites and environments in SV/UVM and C (as needed), including CPU/BFM(VIP)-based benches.
• Identify functional cover points and assertions; write sequences to achieve coverage goals; close functional and code coverage.

Debug & Quality

• Collaborate closely with design to identify and resolve design errors; perform debug of failures, analyze logs and waveforms, and report observations.
• Improve verification quality by identifying coverage holes, tuning randomization, and adding targeted tests.
• Review and sign off on verification readiness for tape-out.

Methodology, Automation & Reuse

• Automate verification flows/environments to handle multiple design configurations.
• Drive robust constraint/testbench component development, assertions, and regression infrastructure.
• Promote reuse across IP, subsystem, and SoC levels; standardize checks and best practices.

Cross-Functional Collaboration

• Work with architecture, design, DFT/DFD, clock/power, and SoC integration teams to ensure end-to-end verification completeness.
• Support bring-up considerations (boot, reset, clocking, low power) within verification scope.

Qualifications

• BE/B.Tech/ME/M.Tech (or equivalent) in ECE/EEE/CSE.
• 8–15 years of verification experience with successful tape-outs of more than one SoC/subsystem; strong track record mentoring and managing verification teams.
• Strong expertise in:
• System Verilog/UVM; CPU- and BFM(VIP)-based testbenches
• AMBA/CHI protocols: CHI, AXI, AHB, APB; AMBA-based NIC/NoC
• EDA simulation and waveform viewer tools
• Deep understanding of:
• High-speed protocols: PCIe 4/5, LPDDR4/5, GDDR6, SD/eMMC, GbE
• Low-speed peripherals and IO interfaces
• DFT/DFD architectures and implications on verification
• Boot, reset, clocking schemes, and low-power verification
• High-performance SoC architectures and verification at IP/subsystem/SoC levels
• Scripting and automation: Perl, Python, Make, and shell scripting.
• Excellent programming and strong debugging skills.
• Soft skills: mentoring and interpersonal skills; analytical/problem-solving; strong written and oral communication; innovation and automation mindset; time and risk management.

Why Join Us?

• Lead verification for complex, high-performance SoCs with broad ownership from planning to tape-out signoff.
• Work at the core of SEMIFIVE’s platform-driven silicon approach, enabling reuse and scalable methodologies.
• Collaborate with world-class, cross-functional teams across architecture, design, DFT, and Integration.
• Grow as a technical leader by mentoring engineers and driving automation and best practices.
• Be part of a rapidly scaling India design centre delivering first-time-right silicon for global customers.