Semifive India Design Centre, headquartered in Bangalore, is a rapidly growing capability centre responsible for delivering complex, multi-node SoC programs for global customers across the US, Europe, and Asia. The India team owns front-end through back-end execution, including RTL, STA, synthesis, physical design, and signoff for turnkey silicon programs.

Key Responsibilities

SoC Timing & Synthesis Leadership

• Own SoC-level timing architecture and closure for complex, multi-million gate designs.
• Lead top-level STA and synthesis across multiple SoCs running in parallel.
• Define and drive timing budgets, constraints, and closure strategy across blocks, subsystems, and top-level integration.
• Act as the final signoff authority for timing and synthesis quality across all programs.

Execution & Technical Ownership

• Drive multi-mode multi-corner (MMMC) timing signoff, including functional, scan, and low-power modes.
• Own constraint development and validation (SDC) at block and SoC level.
• Lead timing convergence across pre-CTS, post-CTS, and post-route stages.
• Partner closely with physical design, clocking, power, and DFT teams to resolve complex timing challenges.
• Guide synthesis strategy including hierarchical vs flat synthesis, QoR optimization, and ECO methodologies.

Cross-Functional & Foundry Collaboration

• Work closely with RTL, DFT, PD, package, and foundry teams to ensure end-to-end timing closure.
• Interface with foundry and EDA vendors on advanced node timing issues, signoff rules, and best practices.
• Support customer design reviews, timing signoff discussions, and technical escalations.

Methodology & Team Development

• Define and standardize STA and synthesis methodologies across Semifive programs.
• Develop automation, checks, and best practices for scalable and predictable timing closure.
• Mentor and guide STA and synthesis engineers, building strong technical depth within the team.
• Review and approve timing signoff checklists, reports, and tapeout readiness.

Qualifications

• B.E./B.Tech or M.E./M.Tech in Electrical / Electronics / VLSI Engineering.
• 12+ years of experience in STA, synthesis, and timing closure for complex SoCs.
• Proven track record of owning top-level timing closure on multiple successful SoC tapeouts.
• Strong expertise in:
• Static Timing Analysis (PrimeTime or equivalent)
• Synthesis flows (Design Compiler, Fusion Compiler)
• MMMC analysis and advanced constraint development
• Deep understanding of:
• Clocking architectures (multiple clocks, generated clocks, CDC implications)
• Low-power design and timing interactions (UPF/CPF)
• Scan and test-mode timing closure
• ECO flows and late-stage timing fixes
• Experience working on advanced technology nodes (12nm and below).
• Strong debugging, analytical, and problem-solving skills.
• Excellent communication skills with ability to lead cross-functional and global teams.

Why Join Us?

At Semifive, you will play a critical technical leadership role in delivering first-time-right silicon for global customers. Unlike traditional large semiconductor organizations, Semifive offers broad ownership and real impact, where timing and synthesis leaders directly influence architecture, implementation strategy, and final silicon quality.

As part of Semifive India, you will work on multiple complex SoCs, partner with world-class engineering teams across geographies, and help build scalable STA and synthesis methodologies for a rapidly growing organization.

This role offers the opportunity to shape not just individual chips — but how silicon is built at Semifive.