Semifive India Design Centre, headquartered in Bangalore, is a rapidly growing capability centre responsible for delivering complex, multi-node SoC programs for global customers across the US, Europe, and Asia. The India team owns RTL-to-GDS execution, including physical implementation, timing, power, and signoff for turnkey silicon programs.

Key Responsibilities

SoC Physical Implementation Leadership

• Own SoC-level physical implementation strategy and execution for complex, large-scale designs.
• Lead floorplanning, power planning, placement, CTS, routing, and signoff across multiple SoCs running in parallel.
• Act as the technical authority for PnR decisions, QoR trade-offs, and implementation signoff.

Execution & Technical Ownership

• Drive top-level floorplanning and partitioning, including macro placement, IO planning, and hierarchy definition.
• Own power grid architecture, IR/EM planning, and reliability signoff in collaboration with power integrity teams.
• Lead clocking architecture implementation, CTS strategy, and clock QoR optimization.
• Guide routing strategy, congestion mitigation, and late-stage ECO closure.
• Ensure timing, power, and area convergence in partnership with STA and synthesis teams.
• Own physical design signoff readiness, including DRC/LVS, IR/EM, antenna, and reliability checks.

Cross-Functional & Foundry Collaboration

• Work closely with RTL, STA, DFT, package, and foundry teams to ensure end-to-end physical convergence.
• Interface with foundry and EDA vendors on advanced-node implementation challenges and best practices.
• Support customer-facing design reviews, implementation status updates, and technical escalations.
• Collaborate with packaging teams on chip-package interaction (CPI) and IO/bumps planning.

Methodology & Team Development

• Define and standardize PnR methodologies, flows, and checklists across Semifive programs.
• Drive automation, scripting, and flow optimization to improve predictability and turnaround time.
• Mentor and develop physical design engineers and block leads, building strong technical depth.
• Establish tapeout readiness criteria and review physical signoff deliverables.

Qualifications

• B.E./B.Tech or M.E./M.Tech in Electrical / Electronics / VLSI Engineering.
• 12+ years of experience in ASIC physical design and PnR, with ownership of multiple full-chip SoC tapeouts.
• Proven expertise in:
• PnR tools: Cadence Innovus, Synopsys ICC2 / Fusion Compiler, or equivalent.
• Advanced-node physical design challenges (12nm and below).
• Strong hands-on experience in:
• Floorplanning and hierarchical implementation
• Power grid and IR/EM analysis (RedHawk, Voltus, or equivalent)
• Clock tree synthesis and optimization
• Routing congestion analysis and closure
• Physical verification (Calibre, Pegasus)
• Deep understanding of:
• Multi-voltage and low-power design (UPF/CPF)
• Scan and DFT physical integration
• ECO methodologies and late-stage fixes
• Experience working on large, complex SoCs with multiple power and clock domains.
• Strong leadership, debugging, and cross-functional communication skills.

Why Join Us?

At Semifive, the SoC PnR Lead plays a pivotal role in delivering first-time-right silicon. Unlike traditional large semiconductor companies where physical design roles can be narrowly scoped, Semifive offers broad ownership and real technical influence across the entire RTL-to-GDS flow.

You will work on multiple cutting-edge SoCs, partner with world-class teams across geographies, and help shape the physical design methodologies of a rapidly growing global organization.

This role offers the opportunity to define how complex silicon is physically realized at Semifive, while mentoring the next generation of physical design leaders.