Responsibilities:-

Develop and implement Register Transfer Level (RTL) design for digital circuits using Verilog/SystemVerilog/VHDL. Architect and design key functional blocks, ensuring efficient and optimised hardware implementation. Define microarchitecture based on architecture specifications and requirements. Collaborate with system architects and design teams to refine features and performance trade-offs. Work closely with verification teams to ensure functional correctness through simulation, formal verification, and debugging. Support post-silicon debugging and bring-up activities. Performance Optimisation & Power Efficiency. Optimise RTL for power, performance, and area (PPA) trade-offs. Perform timing closure, power analysis, and clock domain crossings (CDC) checks. Collaborate with the physical design team to ensure synthesis, timing closure, and DFT (Design for Testability) requirements. Ensure the RTL is synthesis-friendly and meets target constraints. Work with cross-functional teams (architecture, verification, physical design, software, validation). Document design specifications, architecture, and implementation details

Requirement:-