SoC Architect – Secure Computing

Locations: Bangalore / Remote ( Any where in India )

Job Description:

We are seeking an experienced SoC Architect with a strong background in secure

computing to help architect the next-generation AI inference SoC. You will focus on the

definition and development of a secure I/O and compute subsystem, ensuring robustness

from power-on to runtime in a virtualized, multi-tenant deployment.

This role focuses on designing and integrating security features such as Root of Trust

(RoT), secure boot and firmware upgrades, key lifecycle management, encryption

engines, and isolation mechanisms at both the firmware and hardware layers. You will

define and drive architectural specifications for secure PCIe interfaces, memory

encryption support (e.g., for LPDDR or HBM), and establishing chain of trust between RISC-

V cores.

Responsibilities:

• Define and develop secure boot flows, authentication, and RoT frameworks for

PCIe-based AI accelerator cards.

• Define and develop the verification plan for the secure sub-system of the SoC

including but not limited to secure boot, firmware upgrade, key lifecycle

management, and threat vector modeling.

• Architect SoC-level and IP-level protections, including memory encryption and

secure debug interfaces.

• Integrate security-specific IPs such as crypto engines, key managers, and security

monitors/sensors.

• Collaborate with firmware, system software, and verification teams to ensure

secure HW/SW co-design

• Ensure compliance with security standards and best practices (e.g., NIST, FIPS, PSA

Certified).

• Participate in silicon bring-up and validation of secure features.

Required Background:

• BS/MS/Ph.D. in EE, CS, or related field with 10-25+ years of SoC design experience.• Strong knowledge of hardware security architecture, trusted execution

environments, and secure memory.

• Experience with secure boot flows, key provisioning, secure debug/test interfaces.

• Familiarity with PCIe Gen 4/5, SR-IOV, and secure virtualization mechanisms.

• Experience with RISC-V SoCs and integrating security features into SoC-level

designs.

• SystemVerilog and UVM-based verification experience a plus.

Contact:

Uday

Mulya Technologies

muday_bhaskar@yahoo.com

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