We are looking for an experienced Signal Integrity (SI) Engineer with 5+ years of hands-on experience to lead and support signal integrity analysis at both PCB and package levels.

The role focuses on high-speed interface simulation, analysis, and optimization for advanced SoCs and systems used in high-performance computing, networking, and datacenter applications.

The position involves close collaboration with PCB, package, silicon, and system teams to ensure robust, manufacturable high-speed designs across multiple platforms.

Key Responsibilities

Perform signal integrity simulations and analysis at board and package levels using Ansys HFSS and 3D Layout tools.

Analyze and optimize high-speed serial and parallel interfaces, including Ethernet, PCIe, DDR, and other advanced protocols.

Support channel modeling, including transmitter, receiver, package, and board interconnects.

Evaluate and address loss, impedance discontinuities, crosstalk, reflections, and jitter.

Validate 3D EM models for packages, connectors, vias, and critical interconnect structures.

Support IBISAMI / SerDes channel analysis, including eye diagrams, BER, and compliance checks.

Correlate simulation results with lab measurements and system bringup findings when available.

Provide SI design guidelines and recommendations for stackups, routing, and materials.

Collaborate closely with PCB, package, PI, system, and silicon teams to resolve signal quality issues.

Contribute to debugging and rootcause analysis of high-speed failures during validation and bringup.

Qualifications

5+ years of experience in signal integrity analysis at board and/or package levels.

Strong hands-on experience with Ansys HFSS and 3D Layout simulation tools.

Solid understanding of high-speed signal integrity fundamentals , including transmission lines, Sparameters, crosstalk, return loss, insertion loss, and jitter.

Experience with high-speed interfaces such as: Ethernet 112G / 224G , PCIe Gen5 / Gen6 / CPO( co-package optics) and other advanced protocols

Ability to work effectively in a cross-functional hardware development environment .

Additional Experience (Advantage)

Packageboard cosimulation experience.

Familiarity with IBIS / IBISAMI models and SerDes compliance flows.

Familiarity with the COM–channel operating margin

Familiarity with Seasim – Pcie channel simulation tool

Lab measurement experience (TDR, VNA, oscilloscope eye measurements).

Experience with advanced packaging technologies (FCBGA, interposer, chiplets).

Scripting or automation experience (Python, MATLAB).

Skills :

Strong analytical, problem-solving, and communication skills.

Strong analytical, problem-solving, and communication skills.

Education:

B.Sc. or M.Sc. in Electrical Engineering or a related field.