Role:

Own complete RTL design for complex SoC or major subsystem blocks—from micro‑architecture to tape out and silicon bring‑up.

Responsibilities:

• Define micro‑architecture and develop high‑quality synthesizable System Verilog/Verilog RTL.
• Lead design brings‑up, integration, and close timing/power/area with synthesis and PnR teams.
• Run design reviews, fix bugs, and support silicon validation and post‑silicon debug.

Must‑Have:

• 8+ years hands‑on ASIC RTL design (FPGA not counted).
• Multiple production ASIC tape outs owning major SoC/subsystem functions.
• Strong RTL Coding/micro‑architecture skills, low‑power design.

Job Location: Bangalore (WFO)