Proxelera

Proxelera helps semiconductor teams reduce risk and accelerate silicon delivery with end-to-end product engineering. It delivers ASIC/SoC design, RTL, verification, FPGA prototyping, and embedded…

AI ChipsChip DesignIP DesignNetworking SiliconProduct EngineeringSemiconductorsSilicon ValidationSystem Softwareproxelera.com

Proxelera

Proxelera helps semiconductor teams reduce risk and accelerate silicon delivery with end-to-end product engineering. It delivers ASIC/SoC design, RTL, verification, FPGA prototyping, and embedded…

AI ChipsChip DesignIP DesignNetworking SiliconProduct EngineeringSemiconductorsSilicon ValidationSystem Softwareproxelera.com

HQBengaluru, IN

Team Size124

Open Jobs6

Total Funding-

Latest FundraiseUnknown

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Senior/Principal ASIC RTL Design Engineer (SoC/Subsystem)

On-SiteChennai, Tamil Nadu, IN

On-Site • Chennai, Tamil Nadu, IN

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My name is Shahid I am reaching out with a role that fits engineers who enjoy real ownership, from shaping micro-architecture to watching their RTL come alive in silicon. If you’re looking for a space where your design decisions actually matter, this one is worth your time.

Job Title

Senior/Principal ASIC RTL Design Engineer (SoC/Subsystem)

Location -Bangalore, Karnataka

Job Description :

Job Summary: Own end-to-end RTL design for complex SoC or large subsystem blocks, from micro-architecture through tapeout and silicon bring-up.

Responsibilities:

Define micro-architecture from specs; write high-quality synthesizable SystemVerilog/Verilog RTL for SoC-level or large subsystems.
Own design bring-up, block/subsystem integration, and close on timing, power, and area with synthesis and PnR teams.

Nice to have:

Exposure to coherency protocols, cache/memory controllers, DDR/PCIe subsystems, security/crypto blocks.
SVA for design-level assertions, performance modeling, or power/perf analysis skills.
Scripting for design productivity (Tcl/Python), used in service of hands-on RTL work.

Best,

Shahid

Drive design reviews, close bugs, and support silicon validation and post-silicon debug.

Collaborate with DV to define test plans, assertions, and coverage goals; support emulation/FPGA only as a secondary validation aid (not counted toward the 8 years).

Must-have qualifications:

8+ years of hands-on ASIC RTL development experience (FPGA work does not count toward the 10 years).

Multiple production ASIC tapeouts owning significant SoC or subsystem functionality (e.g., interconnects, coherency, memory subsystem, high-speed I/O, security, or power-management islands).

Strong SystemVerilog/Verilog RTL and micro-architecture skills, including clock/reset design, low-power techniques (UPF/retention/isolation), and AMBA/standard bus protocols (AXI/ACE/AHB/APB).

Proven collaboration with physical design on synthesis constraints, timing closure, DFT hooks, and ECOs.

Proven silicon bring-up experience for owned blocks/subsystems.