About the Role

We are seeking a highly experienced Senior Staff Physical Design Engineer with a strong background in chip-level implementation and EDA tools. The ideal candidate will have deep expertise in physical design, timing closure, and low-power design.

Qualifications

• 8-10 years of experience in physical design (excluding other areas such as logic design or CAD).
• Strong understanding of EDA implementation for chip design, with hands-on experience in Cadence tools (must-have).
• Strong knowledge of timing concepts and timing closure techniques for chip design.
• Experience with both top-level and block-level physical design is required; experience with hierarchical floorplanning is a plus.
• Proficiency in low-power design concepts and debugging is necessary.
• Experience with EM/IR checks, debugging, and issue resolution, including power grid verification, is required.
• Strong scripting skills in TCL or Python for automation are important.
• Understanding of process concepts is needed for physical verification as part of routing tasks.
• Experience with physical design methodology and flow setup is preferred; this role will involve advanced flow evaluations.
• Additional experience in areas such as PDK management or foundry tapeout processes is a plus

Contact

Uday

uday@mulyatech.com

Mulya Technologies

"Mining the Knowledge Community"