
EnCharge AI provides efficient, low‑power AI computing solutions that let businesses run advanced models from edge devices to the cloud. The company designs analog in‑memory computing chips and pairs…

EnCharge AI provides efficient, low‑power AI computing solutions that let businesses run advanced models from edge devices to the cloud. The company designs analog in‑memory computing chips and pairs…
Founded: 2022
Headquarters: Santa Clara, California
Tech focus: Analog in-memory AI accelerators and software for edge-to-cloud
Recent funding: Series B > $100M (announced Feb 2025)
Energy- and space-constrained AI inference acceleration for edge-to-cloud deployments.
2022
Data and Analytics
21700000
Emergence from stealth with $21.7M
22600000
Raised $22.6M to commercialize chips
100000000+
Series B announced as more than $100M
“Includes both financial and strategic investors such as Tiger Global, Samsung Ventures, CTBC/HH-CTBC, AlleyCorp, and others”
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(www.enchargeai.com)
Senior Staff / Staff Engineer, Static Timing Analysis (STA)
Location: Greater Bengaluru Area (Hybrid-2 days office/3 days home)
About Company:
EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.
Staff / Senior Staff Engineer: Static Timing Analysis (STA) Lead.
We are seeking a high-caliber Staff or Senior Staff Engineer to lead SOC Timing Convergence. This is a critical leadership role for a driven, "go-getter" engineer who excels at navigating the complexities of modern, large-scale SOC designs. You will be the bridge between Architecture, RTL, DFT, and Physical Design to ensure a predictable, high-performance path to tape-out.
The Role
As a lead for SOC Timing or SubChip Timing, you will own the strategy for convergence. You will identify bottlenecks early in the design cycle ("left-shifting") and drive cross-functional alignment to meet aggressive Power, Performance, and Area (PPA) targets.
Key Responsibilities
Requirements & Qualifications
Why Join Us?
You will have the autonomy to define the timing methodology for next-generation silicon. This role offers the opportunity to tackle the industry's toughest frequency and power challenges while building the automation infrastructure that defines our engineering excellence.
Contact
Uday
muday_bhaskar@yahoo.com
Mulya Technologies
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