EnCharge AI

EnCharge AI provides efficient, low‑power AI computing solutions that let businesses run advanced models from edge devices to the cloud. The company designs analog in‑memory computing chips and pairs…

AI ComputeEdge AIEfficiencyHardwareIn-Memory ComputingPerformanceSustainabilityTCOenchargeai.com

EnCharge AI

AI ComputeEdge AIEfficiencyHardwareIn-Memory ComputingPerformanceSustainabilityTCOenchargeai.com

HQSanta Clara, US

Team Size91

Open Jobs797

Total Funding$163M

Latest Fundraiselast year

TL;DR

Founded: 2022 (Princeton University spinout)

Headquarters: Santa Clara (evidence: company described as Santa Clara–based)

Product: Analog in-memory AI accelerators with hardware/software stack for edge-to-cloud

Recent funding: Series B (Feb 13, 2025) > $100M led by Tiger Global

Total funding reported: $162.9M (currency: USD)

Company Overview

Problem Domain

Energy-efficient AI inference for edge and cloud (power-constrained applications, on-device/edge deployments).

Founded

2022

Industry

Data and Analytics

Funding Track Record

Series A- 2022-12-14

21700000

Reported $21.7M; participants included AlleyCorp, Scout Ventures, Silicon Catalyst Angels and others.

Post-seed / growth (reported round)- 2023-12-05

22600000

Reported $22.6M round (brought total to ~$45M at that time); participants included VentureTech Alliance, RTX Ventures, ACVC Partners, Anzu Partners, S5V, AlleyCorp, Scout and Silicon Catalyst Angels.

Series B- 2025-02-13

100000000

Reported as more than $100M Series B led by Tiger Global.

Investor Signal

“Includes strategic and financial investors such as Tiger Global, VentureTech Alliance (TSMC-related), RTX Ventures, Samsung Ventures and a mix of VC and corporate backers”

Founders

What we do

Join the Team

Senior Staff Engineer, Static Timing Analysis (STA)

HybridGreater Bengaluru Area, IN

Hybrid • Greater Bengaluru Area, IN

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(www.enchargeai.com)

Senior Staff / Staff Engineer, Static Timing Analysis (STA)

Location: Greater Bengaluru Area (Hybrid-2 days office/3 days home)

About Company:

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.

Staff / Senior Staff Engineer: Static Timing Analysis (STA) Lead.

We are seeking a high-caliber Staff or Senior Staff Engineer to lead SOC Timing Convergence. This is a critical leadership role for a driven, "go-getter" engineer who excels at navigating the complexities of modern, large-scale SOC designs. You will be the bridge between Architecture, RTL, DFT, and Physical Design to ensure a predictable, high-performance path to tape-out.

The Role

As a lead for SOC Timing or SubChip Timing, you will own the strategy for convergence. You will identify bottlenecks early in the design cycle ("left-shifting") and drive cross-functional alignment to meet aggressive Power, Performance, and Area (PPA) targets.

Key Responsibilities

Requirements & Qualifications

Experience: 9 to 14 years of hands-on experience in STA and Timing Closure on advanced process nodes (7nm, 5nm, or below).

Why Join Us?

You will have the autonomy to define the timing methodology for next-generation silicon. This role offers the opportunity to tackle the industry's toughest frequency and power challenges while building the automation infrastructure that defines our engineering excellence.

Contact

Uday

muday_bhaskar@yahoo.com

Mulya Technologies

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Timing Convergence Leadership: Drive full-chip SOC timing closure across all corners and modes (func, shift, capture, etc.).

Cross-Functional Coordination: Partner with Architecture to validate timing feasibility, RTL to optimize logic structures, and DFT to streamline test-mode timing.

Left-Shift Strategy: Proactively identify and resolve structural timing issues, congestion, and high-latency paths early in the RTL/Synthesis phase to ensure predictable physical design execution.

Advanced Analysis: Perform complex timing tasks including CPPR/CRPR analysis, NoC (Network-on-Chip) timing, and constraint validation (SDC).

Automation & Agility: Architect and build sophisticated automation utilities (Tcl, Python, Perl) to accelerate timing sign-off, reduce manual audits, and improve schedule agility.

PPA Optimization: Drive best-in-class PPA by guiding physical design teams on floorplanning, clock tree synthesis (CTS) strategies, and placement optimizations.

Critical Thinking: Proven ability to debug complex timing violations, identify root causes (e.g., data-to-clock skew, crosstalk), and propose architectural or physical solutions.

Technical Mastery: * Expertise in industry-standard sign-off tools (e.g., PrimeTime, Tempus). Preferable Tempus tool.

Deep understanding of Multi-Mode Multi-Corner (MMMC) challenges and Hierarchical vs. Flat timing closure.

Proficiency in SDC/CDC constraints.

Soft Skills: Strong leadership presence with the ability to influence cross-functional teams and drive execution in a fast-paced environment.

Education: B.Tech/M.Tech in Electrical/Electronics Engineering or a related field.