Responsibilities

• Design and sign-off of multiple IPs to customer specifications.
• Collaborate with other designers and teams for seamless system integration.
• Drive design reviews and provide technical mentorship to junior engineers.
• Support product characterization, debugging, and failure analysis as required.

Qualifications

• Self-sufficient and proficient in tool usage and design fundamentals.
• Proven track record in managing the co-design and integration of circuits/IPs.
• Experience in PMU and Security system design is a plus.
• Strong IP-level system and transistor-level design experience of mid to high complexity IPs (e.g., SAR ADCs, Sigma-delta ADCs, PLLs).
• Comprehensive design experience of fundamental analog building blocks (e.g., BGs, LDOs, POR, low spec DACs, ADCs).
• Design experience in low geometry CMOS processes (40/28/22/16/12nm; nice to have 7nm and lower).
• Ability to provide technical guidance and training to junior engineers.
• Strong problem-solving skills and a rigorous approach to work and documentation.
• Confident in customer-facing meetings and communications.

Benefits

• Friendly, supportive, and inclusive working environment.
• Flexible work hours to fit personal commitments.
• Hybrid and remote working options.
• Professional development and professional society membership.
• Company share options.
• 25 days’ annual leave with the option to purchase additional days.
• Company pension scheme (with a salary sacrifice option).
• Private health insurance (including optical and dental cover).
• Life Assurance.
• Cycle-to-work scheme.
• Employee Assistance Programme – free wellbeing and health services.

If the above role matches your experience, skills, and motivations, we would love to hear from you.