
Tsavorite Scalable Intelligence is revolutionizing enterprise AI with its innovative chiplet technology, enabling scalable and sustainable AI compute solutions. Their products include advanced…

Tsavorite Scalable Intelligence is revolutionizing enterprise AI with its innovative chiplet technology, enabling scalable and sustainable AI compute solutions. Their products include advanced…
Founded: 2023
Headquarters: Milpitas, California
Product focus: Chiplet-based Omni Processing Unit (OPU) and TAOS software stack for scalable AI compute
Recent funding: Series A announced Mar 7, 2025 (~$17.9M reported)
Employees (reported): 85
Scalable, power-efficient AI training and inference for enterprise deployments
2023
Data and Analytics
17900000
Reported on-list entries indicate a Series A announced March 7, 2025 for approximately $17.9M.
| Company |
|---|
Senior Simulation Engineer
LOCATION: GREATER BENGALURU AREA
Company Description
We are looking for exceptional talent and leadership to join Fast Growing Startup into Scalable Intelligence, the world’s first company developing Agentic Silicon for powering the future of AI.
Founded in 2023, We have deep customer engagements across America, Europe, and Asia, and demonstrated functional prototypes to prove our concept and vision.
Senior Simulation Engineer
Location: Bangalore, Karnataka
Team: Hardware Architecture / Systems Modeling
The Mission
As a Senior Simulation Engineer, you will be the bridge between abstract AI algorithms and physical silicon. You’ll build the high-performance modeling infrastructure used to validate our next-generation accelerators, ensuring our hardware can handle massive computational demands before a single transistor is laid.
Key Responsibilities
Architectural Modeling: Develop and maintain cycle-accurate and functional simulators (C++/SystemC) for specialized compute engines.
Performance Analysis: Identify bottlenecks in data movement, memory hierarchy (HBM/SRAM), and interconnects using trace-driven and execution-driven simulations.
Hardware Co-design: Collaborate with the Compiler and Kernel teams to profile workload mapping and optimize the hardware ISA for maximum throughput.
Validation & Correlation: Validate simulator accuracy against RTL models and silicon measurements to ensure high-fidelity performance projections.
Required Qualifications
Education: BS/MS in Computer Engineering, Computer Science, or Electrical Engineering.
Systems Expertise: 5+ years of experience in computer architecture and performance modeling.
Coding Proficiency: Advanced C++ (templates, STL) and experience using Python for scripting and data analysis.
Architecture Depth: Strong understanding of memory sub-systems, and SIMD/systolic array architectures.
Bonus Points
Experience with machine learning frameworks or neural network graph compilers.
Knowledge of GPU architectures or specialized NPU accelerators.
Familiarity with SystemC or TLM (Transaction Level Modeling).
Contact
Uday
muday_bhaskar@yahoo.com
www.mulyatech.com
"Mining the Knowledge Community"
Your next opportunity is in here somewhere. Sign up to explore 52,000+ startups and their open roles. No spam. No gamification. Just jobs.
52,000+
Startups
65,000+
Open Roles
1,400+
New This Week