• Technical ownership of logic design and validation of various functional blocks of CPU, IPs, and/or SoC
• Document microarchitecture specifications and test plans; drive reviews of AI-generated specs and test plans
• Design in-house hardware IPs, including logic synthesis, timing closure, power optimization, area reduction, and performance targets
• Develop validation content including UVM and SystemVerilog testbenches, directed and constrained random tests, SystemVerilog assertions, and functional coverage
• Apply agentic workflows to generate synthetic data for logic design and verification

Required Qualifications

• BS in Electrical Engineering or a related technical field
• 5+ years of experience in CPU, graphics, or SoC design and validation
• Strong knowledge of CPU, IP, and SoC architecture
• Experience with logic design, synthesis, timing closure, low-power design, multi-clock domains, and area optimization
• Knowledge of verification methodologies (test plan development, test generation/debug, assertion-based verification, coverage analysis and closure)
• Experience with SystemVerilog and UVM
• Experience with C/C++ and assembly
• Experience with Python or other scripting languages
• Strong cross-functional communication skills across multidisciplinary teams
• Business-fluent English

Nice To Have

• Experience with emulation and gate-level verification
• Experience with backend flow and physical design

What We Offer

• Work on foundational, unsolved problems at the intersection of AI and hardware
• Real ownership with direct impact on core product capabilities
• Collaborate with a high-caliber team across AI, cloud, and semiconductor design
• A culture of innovation, precision, and impact
• Competitive compensation package, including equity participation