We are now looking for a Senior Power Verification Engineer. NVIDIA is seeking elite ASIC Verification Engineers to verify the design and implementation of low power features for the world’s leading Smart-NICs and DPUs which help accelerate network performance while reducing the CPU overhead of Internet Protocol (IP) packet transport, freeing more processor cycles to run applications. These networking processors also embed innovative hardware engines that offload and accelerate security with in-line encryption/decryption. With unmatched RDMA over Converged Ethernet (RoCE) performance, NVIDIA Smart-NICs and DPUs deliver efficient, high-performance remote direct-memory access (RDMA) services to bandwidth- and latency-sensitive applications!The Networking Chip Design in India is a new team which is growing at a fast pace! - Work on structural and functional verification of low power aspects of NVIDIA’s family of smartNICs and DPUs. - Come up with test plans and coverage plans of these features. - Write test cases, test bench components like assertions and coverage points, and own verification convergence. - Collaborate with system level and unit level teams to cover the features well from functional, electrical, performance, and noise aspects. - Be responsible for debugging waves to analyse power consumed by unit IP’s. - Work with architects, designers, pre- and post-silicon verification teams, synthesis, timing and back-end teams to accomplish your tasks. - Validate/Correlate the effectiveness of the low power features on silicon. - BS/MS or equivalent experience with specialisation related to Low Power techniques and Verification. - 5+ years of experience. - Fundamental understanding of power basics including transistor-level leakage/dynamic characteristics of VLSI circuits. - Knowledge of power intent formats - UPF/CPF. - Experience in Static Power check - tools like VCLP/MVRC or similar. - Hands-on knowledge in Power aware dynamic verification - NLP/MVSIM or similar tools. - Experience in design and verification tools (VCS, XCelium or equivalent simulation tools, Verdi, Indago or other debug tools). - Familiarity with low power design techniques such as multi VT, Clock gating, Power gating, and Dynamic Voltage-Frequency Scaling (DVFS). - Exposure to Cluster/Sub-system/Fullchip/SOClevel verification environments - Prior experience of SmartNICs (or DPU) and/or high-speed interconnects. - Good software programming skills. Python/Perl/C++ preferred. - Confident debugging and problem-solving skills. - Good interpersonal skills and ability & desire to work as an excellent teammate. Widely considered to be one of the technology world’s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com/ NVIDIA is committed to encouraging a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation. JR1997923