Senior PIC Test Engineer

Role Overview

We are seeking an experienced PIC Test Engineer with deep expertise in wafer-level optical and electrical test for Photonic Integrated Circuits (PICs). This role will own the test strategy and execution across the full product lifecycle—from early silicon bring-up through high-volume manufacturing (HVM).

The ideal candidate is a recognized technical authority in test architecture, PIC Design-for-Test (DFT), yield learning, and factory scalability, with proven leadership in driving robust wafer-level test solutions across multiple technology nodes and product families.

Key Responsibilities

Wafer-Level Test Strategy & Architecture

 Define and own the wafer-level PIC test roadmap across multiple product lines and technology platforms.

 Architect scalable, high-throughput optical + electrical wafer probe solutions, balancing alignment accuracy, probe stability, and test time.

 Establish release criteria, guard-banding strategy, and wafer test coverage models aligned with product requirements.

First Silicon Bring-Up & Test Content Development

 Lead first-silicon bring-up efforts, including test content definition, limit setting, and characterization flows.

 Drive rapid yield-learning loops in partnership with design, process integration, and fabrication teams.

 Enable fast debug and iteration during early node transitions and new platform ramps.

DFT & PDK Collaboration

 Influence PIC Design-for-Test features and PDK structures to improve wafer-level scalability, including:

o On-chip monitors

o Loopback paths

o Test waveguides

o Calibration structures

 Partner with design teams to embed manufacturable test hooks early in the development cycle.

Yield Ownership & Data-Driven Analysis

 Own wafer-level yield, parametric distributions, and systematic defect learning.

 Perform advanced spatial analytics using wafer maps and statistical methods to separate random vs systematic process issues.

 Lead root-cause investigations related to coupling variation, lithography bias, and process drift.

Manufacturing Readiness & Factory Scale-Up

 Establish golden wafer / golden die methodologies for production stability and tool correlation.

 Partner with foundries and OSATs to qualify wafer-level optical probe infrastructure.

 Drive successful transfer of test flows into volume manufacturing environments with strong cross-tool correlation.

Technical Leadership & Team Development

 Serve as the technical escalation point during yield crises and manufacturing transitions.

 Mentor and develop junior engineers, setting engineering standards and best practices across wafer-level test programs.

 Multiply organizational impact through scalable infrastructure, DFT influence, and test standardization.

Qualifications

Required

 10+ years of experience in PIC test engineering, wafer-level probing, or photonics manufacturing test.

 Proven ownership of wafer-level optical/electrical test strategy from R&D through HVM.

 Expertise in:

o Wafer-level optical probing

o Probe card qualification

o Yield learning and spatial analysis

o Test time optimization

o Foundry engagement and factory transfer

Preferred

 Experience with high-speed optical and electrical testing of photonic integrated circuits or optical transceivers.

 Experience influencing PIC DFT and collaborating closely with PDK development teams.

 Strong background in high-volume semiconductor or photonics manufacturing ecosystems.

 Demonstrated leadership in scaling test infrastructure across multiple nodes and product families.