
Proxelera helps semiconductor teams reduce risk and accelerate silicon delivery with end-to-end product engineering. It delivers ASIC/SoC design, RTL, verification, FPGA prototyping, and embedded…

Proxelera helps semiconductor teams reduce risk and accelerate silicon delivery with end-to-end product engineering. It delivers ASIC/SoC design, RTL, verification, FPGA prototyping, and embedded…
We are hiring a hands on Physical Design Lead who can take ownership of complex blocks and close them with confidence. If timing closure excites you more than presentations, this is your space.
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The Mandate
Execute block-level physical design from floorplan to GDS
Drive placement, CTS, routing, and PPA optimization
Close timing across corners with strong setup/hold discipline
Resolve congestion, SI, and power integrity challenges
Run signoff checks including DRC, LVS, IR, EM
Collaborate closely with RTL, STA, and DFT teams
Improve flow efficiency through scripting and automation
The Profile
7–13 years of ASIC Physical Design experience
Strong hands-on expertise in advanced nodes (16nm and below preferred)
Proven timing closure experience on high-performance designs
Experience with ICC2 / Fusion Compiler / Innovus
Scripting knowledge (Tcl / Python preferred)
Exposure to low-power design (UPF, power gating) is an advantage
Execution-focused. Technically demanding. Tapeout-driven.