BITSILICA is a rapidly growing global semiconductor design services organization with over 500 professionals serving 25+ clients across India, USA, Singapore, Malaysia, and Vietnam. They specialize…
BITSILICA is a rapidly growing global semiconductor design services organization with over 500 professionals serving 25+ clients across India, USA, Singapore, Malaysia, and Vietnam. They specialize…
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Frontend Developer
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Contract • Berlin, DE
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Internship • Manchester, GB
Mobile Developer
Full-timeAmsterdam, NL
Full-time • Amsterdam, NL
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Full-timeNew York, US
Full-time • New York, US
Technical Writer
Part-timeHamburg, DE
Part-time • Hamburg, DE
Software Engineer
Full-timeNovi Sad, RS
Full-time • Novi Sad, RS
4+ years of experience in Physical Design Implementation
Perform block level physical implementation tasks from RTL to GDSII including synthesis, floorplanning, power planning, placement, Clock Tree Synthesis (CTS) and routing.
Proven track record with advanced nodes of 3nm/4nm/5nm/7nm with successful tapeouts
Perform sign-off analysis and closure on Static Timing Analysis (STA), formal verification (LEC), power analysis (EMIR), and physical verification (DRC/LVS/ERC) for tapeout.
Optimize designs for Performance, Power, and Area (PPA) by improving congestion, timing, and power consumption.
Experience with EDA tools in DC/Genus, ICC2/FC/Innovus, PT/Tempus, Calibre/ICV/Pegasus.
