
Proxelera helps semiconductor teams reduce risk and accelerate silicon delivery with end-to-end product engineering. It delivers ASIC/SoC design, RTL, verification, FPGA prototyping, and embedded software, including IP design and post-silicon validation. The company performs physical design, fab interfacing, and silicon productization, leveraging SystemVerilog, UVM, Python, C/C++, Linux, and Yocto. It supports collaboration with hardware teams and offers outcome-based engagements and royalty-based models, serving global semiconductor customers. With over 190 engineers across Bengaluru and Mysuru and global sales in the USA and Japan, Proxelera scales turnkey chip design projects.

Proxelera helps semiconductor teams reduce risk and accelerate silicon delivery with end-to-end product engineering. It delivers ASIC/SoC design, RTL, verification, FPGA prototyping, and embedded software, including IP design and post-silicon validation. The company performs physical design, fab interfacing, and silicon productization, leveraging SystemVerilog, UVM, Python, C/C++, Linux, and Yocto. It supports collaboration with hardware teams and offers outcome-based engagements and royalty-based models, serving global semiconductor customers. With over 190 engineers across Bengaluru and Mysuru and global sales in the USA and Japan, Proxelera scales turnkey chip design projects.
Job Role: You’ll lead full-custom memory layout work for SRAM compilers, owning layout creation, physical verification, and sign-off quality. This role calls for someone who knows the craft inside out and can turn complex circuits into clean, high-quality layouts. Responsibilities: Full-custom memory layout development for SRAM compiler blocks Complete physical verification across EM, IR, LVS, DRC and related flows Work closely with circuit, architecture, and verification teams Drive layout quality, constraints, and design-rule adherence Support optimization, debug, and design-rule closure Qualifications: MTech/BTech in ECE or related field 7+ years of hands-on SRAM compiler layout experience Strong grounding in full-custom memory layout and sign-off verification flows