Senior Director, Digital Hardware Design | EnCharge AI · Teeming.ai
EnCharge AI
EnCharge AI provides efficient, low‑power AI computing solutions that let businesses run advanced models from edge devices to the cloud. The company designs analog in‑memory computing chips and pairs…
AI ComputeEdge AIEfficiencyHardwareIn-Memory ComputingPerformanceSustainabilityTCOenchargeai.com
EnCharge AI
EnCharge AI provides efficient, low‑power AI computing solutions that let businesses run advanced models from edge devices to the cloud. The company designs analog in‑memory computing chips and pairs…
AI ComputeEdge AIEfficiencyHardwareIn-Memory ComputingPerformanceSustainabilityTCOenchargeai.com
HQSanta Clara, US
Team Size85
Open Jobs424
Total Funding$163M
Latest Fundraiselast year
TL;DR
Founded: 2022
Headquarters: Santa Clara, California
Tech focus: Analog in-memory AI accelerators and software for edge-to-cloud
Recent funding: Series B > $100M (announced Feb 2025)
Company Overview
Problem Domain
Energy- and space-constrained AI inference acceleration for edge-to-cloud deployments.
Founded
2022
Industry
Data and Analytics
Tech Stack
Analog in-memory compute chips
Hardware systems for dense matrix operations
Software stack for inference/model deployment
Funding Track Record
Seed / Series A- 2022-12-14
21700000
Emergence from stealth with $21.7M
Undisclosed round- 2023-12-05
22600000
Raised $22.6M to commercialize chips
Series B- 2025-02-13
100000000+
Series B announced as more than $100M
Investor Signal
“Includes both financial and strategic investors such as Tiger Global, Samsung Ventures, CTBC/HH-CTBC, AlleyCorp, and others”
Founders
What we do
Join the Team
Senior Director, Digital Hardware Design
HybridGreater Bengaluru Area, IN
Hybrid • Greater Bengaluru Area, IN
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Job Title: Senior Director, Digital Hardware Design
Bangalore
We are a well-funded US AI hardware startup building next-generation compute platforms that bring advanced, secure, and sustainable AI from the edge to the cloud. Backed by groundbreaking R&D in computation physics, ultra-efficient circuits, and scalable architectures, we are redefining what’s possible in performance and energy efficiency. Join a team of industry veterans pushing the boundaries of AI and shaping technology that will serve humanity at global scale.
Job Description:
We are seeking a Senior Director of Digital Hardware Design to lead and expand our SoC design organization in Bangalore. This is a hands-on technical leadership role responsible for scaling a world-class front-end design team, driving execution across multiple SoC programs, and collaborating closely with architecture, verification, physical design, firmware, and software teams. You will play a pivotal role in defining and delivering ultra-efficient, next-generation AI compute platforms.
Responsibilities
Lead and mentor a high-performing team of SoC design engineers across RTL design, IP logic development, and SoC/subsystem integration.
Requirements
Contact:
Uday
Mulya Technologies
muday_bhaskar@yahoo.com
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Own IP, subsystem, and full-chip design and integration from concept through tape-out.
Partner closely with Architecture, DV, PD, Firmware, and Post-Si teams to deliver high-quality silicon on aggressive schedules.
Drive project planning, resourcing, task allocation, and execution tracking for multiple concurrent programs.
Recruit, develop, and retain top-tier engineering talent.
Establish and enforce best practices for RTL development, design quality, verification readiness, low-power design, physical-awareness, and documentation.
Participate in design, micro-architecture, DV, and PD reviews to ensure scalability, performance, and power/area efficiency.
Coordinate seamlessly with global teams across geographies to ensure design convergence and alignment.
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
20–25 years of experience in SoC/ASIC development with at least 8+ years in technical leadership or engineering management.
Proven expertise in front-end RTL design using Verilog/SystemVerilog.
Strong experience with UCIe or similar chiplet protocols, and PCIe and/or CXL.
Deep understanding of interconnect protocols (AXI/CHI), memory systems (DDR, HBM), and caching/coherency architectures.
Broad experience with SoC integration, clock/power/reset domains, and IP/PHY integration.
Experience with ML/AI accelerators, GPUs, CPUs (RISC-V or ARM), and advanced low-power design techniques.
Familiarity with synthesis, STA, design constraints, and physical-design handoff requirements.
Strong understanding of the full silicon development lifecycle from architecture/spec through GDS/tape-out.
Exceptional communication, leadership, and cross-functional collaboration skills.
Experience leading and collaborating with geographically distributed teams.
