Responsibilities

• Lead and mentor a high-performing team of SoC design engineers across RTL design, IP logic development, and SoC/subsystem integration.
• Own IP, subsystem, and full-chip design and integration from concept through tape-out.
• Partner closely with Architecture, DV, PD, Firmware, and Post-Si teams to deliver high-quality silicon on aggressive schedules.
• Drive project planning, resourcing, task allocation, and execution tracking for multiple concurrent programs.
• Recruit, develop, and retain top-tier engineering talent.
• Establish and enforce best practices for RTL development, design quality, verification readiness, low-power design, physical-awareness, and documentation.
• Participate in design, micro-architecture, DV, and PD reviews to ensure scalability, performance, and power/area efficiency.
• Coordinate seamlessly with global teams across geographies to ensure design convergence and alignment.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
• 20–25 years of experience in SoC/ASIC development with at least 8+ years in technical leadership or engineering management.
• Proven expertise in front-end RTL design using Verilog/SystemVerilog.
• Strong experience with UCIe or similar chiplet protocols, and PCIe and/or CXL.
• Deep understanding of interconnect protocols (AXI/CHI), memory systems (DDR, HBM), and caching/coherency architectures.
• Broad experience with SoC integration, clock/power/reset domains, and IP/PHY integration.
• Experience with ML/AI accelerators, GPUs, CPUs (RISC-V or ARM), and advanced low-power design techniques.
• Familiarity with synthesis, STA, design constraints, and physical-design handoff requirements.
• Strong understanding of the full silicon development lifecycle from architecture/spec through GDS/tape-out.
• Exceptional communication, leadership, and cross-functional collaboration skills.
• Experience leading and collaborating with geographically distributed teams.

Contact:

Uday

Mulya Technologies

muday_bhaskar@yahoo.com

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