Job Title: Senior Hardware Verification Engineer

Location: Cambridge, England, United Kingdom (Hybrid possible inside the UK)

About the Role: We are seeking a seasoned Design Verification designer with a strong background in building testbenches and writing test sequences for complex IPs. The ideal candidate will play a key role in shaping our technology portfolio, bringing expertise and creativity to our solutions

Responsibilities :

• Collaborate with design and architecture teams to create test plans for highly configurable IPs meant to provide interconnectivity between components across an SOC, chiplet or multi chiplet systems
• Write UVM/SystemVerilog code to implement the test plan, checkers and scoreboards
• Collaborate with software teams to define and implement configurable testbenches
• Work with design and DV engineers to implement the test plan, debug failures, close coverage, etc.

Qualifications:

• BS/MS in Electrical Engineering, Computer Engineering or Computer Science
• 8+ years and current hands-on experience in block-level/IP-level/SOC-level verification
• Proficiency in Verilog, SystemVerilog

rich.goldstein@bayasytems.com