Job Summary:
We are seeking a skilled
Design Verification Engineer
to drive the functional verification of semiconductor IPs and SoC platforms. The role involves developing robust verification environments, executing comprehensive test plans, and ensuring high-quality design signoff through thorough validation and coverage closure.
Key Responsibilities:
o Develop and maintain verification environments using SystemVerilog and UVM methodologies.
o Create detailed verification plans and test strategies based on design specifications.
o Execute regression suites, analyze results, and debug failures.
o Develop and utilize assertions to improve verification quality.
o Perform functional and code coverage analysis and drive coverage closure.
o Verify complex protocols and interfaces (e.g., PCIe, DDR, USB, Ethernet).
o Collaborate with design, architecture, and validation teams to resolve issues.
o Support verification signoff by ensuring completeness and quality of verification metrics
Qualifications & Experience:
Bachelor’s or Master’s degree in Electronics / VLSI Engineering or related field.
4+ years of experience in functional verification.
Technical Skills:
o
Hands-on experience with:
−SystemVerilog / UVM
−Simulation and debug tools
o
Strong understanding of:
−Functional verification methodologies
−Assertions (SVA) and coverage-driven verification
−Protocol verification
Key Competencies:
o Strong debugging and analytical skills.
o Attention to detail and quality-focused approach.
o Effective communication and teamwork skills.
o Ability to work in collaborative and fast-paced environments.
o Ability to manage tasks under tight project timelines.
Preferred Skills:
o Experience with industry-standard protocols such as PCIe, DDR, USB, or Ethernet.
o Exposure to constrained random verification and reusable testbench architecture.
o Familiarity with verification signoff processes and metrics
About CADFEM Group:
For over 40 years, the CADFEM Group has been a global leader in simulation-driven innovation, with a legacy rooted in decades of advancing numerical simulation. Founded in 1985 as an engineering office focused on simulation sales, support, and training, CADFEM has grown to become the world’s largest Ansys Channel Partner, with a presence in over 20 countries.
As part of this international ecosystem, CADFEM APAC, a digital engineering implementation partner, carries forward the same legacy of excellence to the Indian and south-East Asian engineering community. We help organizations leverage Ansys technologies not just for physics-based simulations, but also as a foundation for digital engineering, workflow automation, and AI/ML-integrated CAE solutions to support industries such as Aerospace, Defense, Semiconductors & electronics, Automotive, Healthcare, and more.
We understand that software alone isn’t enough. That’s why we offer a complete ecosystem that includes simulation software, expert consulting, digital engineering services, customized IT and hardware infrastructure, AI-enhanced workflows, ongoing support, and hands-on training—all from a single, trusted source.
visit: cadfem.ai
