Veevx, Inc.

Veevx is a fabless semiconductor company focused on revolutionizing the semiconductor industry by developing ultra-low power products for AI functionality in mobile and edge devices. Their core technology, iRAM, offers data center AI compute performance with significantly reduced power consumption, enabling longer battery life for devices. Veevx aims to bring advanced AI hardware on-device, enhancing user experience by allowing complex models, typically cloud-processed, to run locally. They offer memory and accelerator semiconductors (iRAM and iRAMx) that ASIC companies can co-package and sell into mobile and edge devices, specializing in new memory technology and mixed-signal compute. Their iRAM-based CIM accelerator boasts superior performance efficiency (TOPs/W) compared to traditional implementations.

AIComputeEdge DevicesiRAMMemoryMobileSemiconductorUltra-low Powerveevx.com

Veevx, Inc.

AIComputeEdge DevicesiRAMMemoryMobileSemiconductorUltra-low Powerveevx.com

HQMesa, US

Team Size17

Open Jobs2

Total Funding-

Latest FundraiseUnknown

Join the Team

Senior CPU and SoC RTL Engineer

On-SiteGandhinagar, Gujarat, IN

On-Site • Gandhinagar, Gujarat, IN

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Job description

🚀 We’re Hiring: Senior CPU & SoC RTL Engineer

📍 Location: Gandhinagar, Gujarat

👥 Team: NextGen iRAM Development

We’re building the next generation of iRAM silicon and are looking for an experienced Hardware Engineer to join our growing team.

If you’re passionate about high-performance CPU and SoC design and enjoy working close to silicon, this is an exciting opportunity to make a real impact.

🔹 About the Role

As a Senior CPU & SoC RTL Engineer, you will be responsible for designing and developing our next-generation RISC-V based SoC. You will work across CPU, NOC, and system-level components while optimizing for Performance, Power, and Area (PPA).

You’ll also collaborate closely with Verification and PnR teams to ensure clean, production-ready handoffs.

🔹 What You’ll Do

Design and develop RTL using Verilog, SystemVerilog, or Bluespec SystemVerilog
Architect and implement CPU subsystems, NOC, and SoC components
Optimize designs for PPA
Follow best design practices for CDC-clean, timing-closure friendly designs
Write and execute unit tests before verification handoff

🔹 What We’re Looking For

5+ years of RTL design experience
Strong expertise in Verilog / SystemVerilog
Solid understanding of CPU architecture and SoC design
Experience with timing closure, UPF, SDC, CDC, RDC
Hands-on experience with UVM or Cocotb for unit testing

🔹 Nice to Have

Experience with HLS frameworks like Bluespec SystemVerilog

If you're excited about building cutting-edge silicon and working on next-gen RISC-V systems, we’d love to hear from you!

📩 Apply here or DM me for more details.