Qualifications

• Bachelor’s or Master’s degrees in EE/CS
• 5-10 years of experience in Design Verification
• Proficiency in the SystemVerilog and UVM languages
• Experience with writing test-plans, test benches, and analyzing coverage metrics
• Excellent written and verbal communication skills
• U.S. Citizen, Permanent Resident, or valid work visa

Preferred Qualifications

• Python coding skills, for EDA automation and design parsing
• Proficient in the use of Git (branches, pull requests, merging, rebasing …)
• Knowledge of industry-standard communication protocols (SPI, I2C, AXI, Ethernet, PCIe, DDR5 …)
• Experience with various verification approaches (SystemVerilog, UVM, CocoTB, Formal Verification …)
• Experience with FPGA development and/or debug (Vivado, Vitis, Quartus, ACE …)
• Comfortable working in a dynamic, research-heavy startup environment