Qualifications

• Bachelor’s or Master’s degrees in EE/CS
• 5-10 years of experience in RTL design
• Proficiency in the SystemVerilog language
• Experience with hands-on debugging – simulators, waveform viewing, coverage collection, etc
• Excellent written and verbal communication skills
• Comfortable working in a dynamic, research-heavy startup environment
• U.S. Citizen, Permanent Resident, or valid work visa

Preferred Qualifications

• Python coding skills, for EDA automation
• Proficient in the use of Git (branches, pull requests, merging, rebasing, …)
• Knowledge of industry-standard communication protocols (SPI, I2C, AXI, Ethernet, PCIe, DDR5, …)
• Experience writing timing constraints (SDC/TCL)
• Experience with FPGA development (Vivado, Vitis, Quartus, ACE …)

What will help you thrive

• Knowledge of open-source tools and contribution practices (Verilator, CocoTB, Yosys, …)