NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world! We are seeking an innovative Senior Physical Design & Timing Methodology Engineer to help drive sign-off strategies for the world's leading GPUs and SoCs. This position is a broad opportunity to optimize performance, yield, and reliability through increasingly comprehensive modeling, insightful analysis, and automation. This work will influence the entire next generation computing landscape through critical contributions across NVIDIA's many product lines ranging from consumer graphics to self-driving cars and the growing domain of artificial intelligence. We have crafted a team of highly motivated people whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. If you are fascinated by the immense scale of precision, craftsmanship, and artistry required to make billions of transistors function on every die at technology nodes as deep as 3 nm, this is an ideal role. What You Will Be Doing * Collaborate with technology leads, circuits and systems teams, VLSI physical design, and timing engineers to define and deploy the most sophisticated strategies of signing off timing in design for world-class silicon performance. * Understand corner case timing sign-off risks in the latest 3nm and deeper technology nodes. Develop strategies to mitigate and margin for them. * Develop tools and methodologies to improve design performance, predictability, and silicon reliability beyond what industry standard tools can offer. * Extensively work with our ASIC Physical Design team to help develop methodologies, flows, and tools across a wide spectrum of domains - STA, constraints, floorplanning, timing and power optimization. * Develop world class work flow solutions to aid analysis and improve flow efficiency. What We Need To See * Master’s Degree in Electrical Engineering, Computer Science, or Computer Engineering or equivalent work experience * 4+ years of relevant work experience * Deep understanding of backend design process, especially advanced STA. * In depth understanding of PT and/or Tempus * Expertise in coding -- TCL, Perl, Python. C++ is a plus! * Strong communication and interpersonal skills Ways To Stand Out From The Crowd * Expertise in developing advanced STA flows JR1995670