
Leading supplier of end-to-end high speed Ethernet and InfiniBand intelligent interconnect solutions and services.

Leading supplier of end-to-end high speed Ethernet and InfiniBand intelligent interconnect solutions and services.
Company: NVIDIA
Core focus: Accelerated computing and AI infrastructure (GPUs, data center and AI systems, edge/robotics, automotive)
Founded: April 1993
Public company / Investor relations: Maintains an active investor relations portal with quarterly results and presentations
High-performance graphics, machine learning/AI acceleration, and full-stack AI infrastructure for enterprise, cloud and edge use cases.
1993
Semiconductors / AI infrastructure
Historical financing and IPO-related information are documented on financial profiles; NVIDIA also deploys strategic investments in startups (examples reported)
$2B
Reported $2B investment to support CoreWeave's AI compute expansion
Come be a part of new process technology adoption by joining NVIDIA's Advanced Technology Group! Work as part of the advanced technology team to optimize design tradeoffs and methodology on next generation CMOS technology. We are looking for a Senior ASIC Synthesis Engineer to join our dynamic and growing team! If you are problem solver and highly motivated individual searching for a collaborative and exciting role, join us today. We encourage applicants with a history of proven success working in a multicultural and diverse environment. NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities which are hard to solve, that only we can pursue, and that matter to the world. This is our life’s work, to amplify human inventiveness and intelligence. What You'll Be Doing - As a Front-End ASIC Synthesis Engineer, you will own RTL synthesis and gate level optimization tasks - Collaboration with physical design to address timing, area, congestion tradeoffs - Drive timing closure and power/area optimization across multiple design blocks - Work with DFT and Verification teams to ensure functional and timing correctness What We Need To See - BS or MS in Electrical Engineering, Computer Engineering, or equivalent experience. - 8+ years of experience in front-end ASIC synthesis and integration. - Deep understanding of Verilog RTL design and digital design principles. - Proven experience with industry-standard EDA tools for synthesis (e.g., Synopsys Design Compiler). - Hands-on experience with timing analysis, constraint management, and post-synthesis ECO flows. - Solid background in low-power and high-performance design optimization techniques. - Familiarity with formal verification tools (e.g., Formality/Conformal LEC) and methodologies. Ways To Stand Out From The Crowd - Knowledge of DFT/Test logic including JTAG, scan, high speed I/O loopback, and memory BIST. - Have proficiency in programming (Python, Perl, Tcl). NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and talented people in the world working for us. If you're creative and autonomous, we want to hear from you. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5. You will also be eligible for equity and benefits . Applications for this job will be accepted at least until August 1, 2025.NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law. JR1999607
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