Proxelera helps semiconductor teams reduce risk and accelerate silicon delivery with end-to-end product engineering. It delivers ASIC/SoC design, RTL, verification, FPGA prototyping, and embedded software, including IP design and post-silicon validation. The company performs physical design, fab interfacing, and silicon productization, leveraging SystemVerilog, UVM, Python, C/C++, Linux, and Yocto. It supports collaboration with hardware teams and offers outcome-based engagements and royalty-based models, serving global semiconductor customers. With over 190 engineers across Bengaluru and Mysuru and global sales in the USA and Japan, Proxelera scales turnkey chip design projects.
AI ChipsChip DesignIP DesignNetworking SiliconProduct EngineeringSemiconductorsSilicon ValidationSystem Softwareproxelera.com
Proxelera
Proxelera helps semiconductor teams reduce risk and accelerate silicon delivery with end-to-end product engineering. It delivers ASIC/SoC design, RTL, verification, FPGA prototyping, and embedded software, including IP design and post-silicon validation. The company performs physical design, fab interfacing, and silicon productization, leveraging SystemVerilog, UVM, Python, C/C++, Linux, and Yocto. It supports collaboration with hardware teams and offers outcome-based engagements and royalty-based models, serving global semiconductor customers. With over 190 engineers across Bengaluru and Mysuru and global sales in the USA and Japan, Proxelera scales turnkey chip design projects.
AI ChipsChip DesignIP DesignNetworking SiliconProduct EngineeringSemiconductorsSilicon ValidationSystem Softwareproxelera.com
We are looking for a Senior / Principal ASIC Design Verification Engineer to lead hands-on verification of complex SoCs or large subsystems, owning execution from verification planning through tapeout and silicon correlation. This role requires deep UVM expertise and strong closure discipline.
Job Description:
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Own end-to-end verification at subsystem or SoC level, including authoring verification plans from specs and micro-architecture and building reusable UVM/SystemVerilog environments from scratch.
Develop constrained-random and directed tests, scoreboards, checkers, coverage models, and SVA assertions to ensure functional correctness.
Drive functional, code, and assertion coverage closure, debug complex failures, and collaborate closely with RTL, architecture, and DFT teams.
Verify standard interfaces and complex subsystems such as AXI/ACE, DDR/PCIe, coherency fabrics, memory and interrupt subsystems, and power states.
Support silicon bring-up and post-silicon correlation, leveraging scripting (Python/Tcl) and low-power or emulation exposure as value adds.
If you’re seeking ownership of verification closure for silicon-critical designs and the opportunity to influence real SoC quality from pre-silicon to post-silicon, this role offers strong technical depth and impact.
