Position Overview We are seeking experienced RTL designers to help define and implement our industry-leading Networking ASIC’s. If you're a highly motivated self-starter eager to solve real-world problems, this is a unique opportunity to shape the future of AI Networking. As part of the Design Group, you will be responsible for defining, specifying, architecting, executing, and productizing cutting-edge Networking chips.

Responsibilities

• Packet buffering, queuing, and scheduling: Work on micro architecture and design implementation of high-speed networking ASIC’s, focusing on latency optimization and quality of service (QoS) support. Prior experience with on-chip memory subsystem and scheduling / arbitration design.
• Implementation and Testing: Implement designs on ASIC platforms, ensuring compliance with industry standards and performance benchmarks. Work with verification team to conduct thorough testing and validation to ensure functionality and reliability.
• Performance Optimization: Analyze and optimize pipelining architectures to improve performance metrics.
• Protocol Support: Provide support for various networking protocols such as Ethernet and IP protocols, and high speed interconnects such as UCIe.
• Troubleshooting and Debugging: Investigate and resolve complex issues related to packet queuing, working closely with cross-functional teams, including system architects, hardware engineers, and firmware developers.

Qualifications

• ME/BE with a minimum of 8-15 years of experience.
• Hands-on knowledge of SystemVerilog and Verilog is mandatory.
• Solid understanding of ASIC design methodologies, including simulation, verification, synthesis, and timing adjustments.
• Proven expertise in designing and optimizing scheduling and QoS mechanisms.
• Experience with Ethernet and IP protocols.
• Strong analytical and problem-solving abilities, with meticulous attention to detail in troubleshooting and debugging complex networking issues.
• Excellent verbal and written communication skills, with the ability to collaborate effectively in a team environment and present technical information to diverse audiences.

Why Join Us? At Eridu AI, you’ll have the opportunity to shape the future of AI infrastructure, working with a world-class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI networking solutions, transforming data center capabilities.

The starting base salary for the selected candidate will be established based on their relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles.

The Pay Range For This Role Is 210,000 - 275,000 USD per year(San Francisco Bay Area)