
Tsavorite Scalable Intelligence is revolutionizing enterprise AI with its innovative chiplet technology, enabling scalable and sustainable AI compute solutions. Their products include advanced robotics and multimodal inference systems, designed for high-performance applications such as streaming video intelligence. The company differentiates itself through power-efficient, supply chain optimized solutions that allow for intuitive software deployment without code changes. With a focus on interoperability and an open ecosystem, Tsavorite positions itself as a leader in the AI space, catering to enterprises looking to leverage AI at scale.

Tsavorite Scalable Intelligence is revolutionizing enterprise AI with its innovative chiplet technology, enabling scalable and sustainable AI compute solutions. Their products include advanced robotics and multimodal inference systems, designed for high-performance applications such as streaming video intelligence. The company differentiates itself through power-efficient, supply chain optimized solutions that allow for intuitive software deployment without code changes. With a focus on interoperability and an open ecosystem, Tsavorite positions itself as a leader in the AI space, catering to enterprises looking to leverage AI at scale.
Founded: 2023
Headquarters: Milpitas, California
Product focus: Chiplet-based Omni Processing Unit (OPU) and TAOS software stack for scalable AI compute
Recent funding: Series A announced Mar 7, 2025 (~$17.9M reported)
Employees (reported): 85
Scalable, power-efficient AI training and inference for enterprise deployments
2023
Data and Analytics
17900000
Reported on-list entries indicate a Series A announced March 7, 2025 for approximately $17.9M.
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TITLE: RTL DESIGN ENGINEER(Principal/Senior Staff Engineer)
LOCATION: GREATER BENGALURU AREA
Company Description
We are looking for exceptional talent and leadership to join Fast Growing Startup into Scalable Intelligence, the world’s first company developing Agentic Silicon for powering the future of AI.
Founded in 2023, We have deep customer engagements across America, Europe, and Asia, and demonstrated functional prototypes to prove our concept and vision.
As a member of Design(RTL) team, you will be responsible for the micro-architecture and design of IPs/Controllers for SoC/SiP designs.
o Perform architectural/design trade-offs for required product features,
performance and system constraints.
o Responsible for defining and documenting design specifications.
o Develop and deliver a fully verified RTL to achieve the design targets and quality sign-off requirements.
o Design and Implement logic functions that enable efficient test and debug.
o Provide Debug support for design verification and post-silicon activities.
Skill and Experience Requirements:
o Minimum 8-14 years industry experience with Master’s degree (preferred) or Bachelors degree in Electrical or Computer Engineering.
o Hand-on experience with micro-architecture and RTL development (System Verilog) for x86/ARM CPU Processors or high-speed custom ASICs/Accelerators
with focus on any one: Cache controller, IO interfaces (PCIe, CXL, Ethernet),
UCIe, Memory controllers, Display, Video encoding/transcoding.
o Good understanding of ASIC design flow including RTL design, verification, logic
synthesis and timing analysis and sign-off quality flows.
o Self-starter with strong interpersonal and communication skills .
Contact
Sumit S. B
sumit@mulyatech.com
www.mulyatech.com
"Mining the Knowledge Community"
Practice Head(Talent Acquisition. Semiconductors Domain)