We are building AI chips that don’t just keep up with the future,they push it forward. If you enjoy shaping microarchitecture, translating ideas into tight, high-quality RTL, and owning complex logic blocks end-to-end, you will feel right at home here.

Your work will sit at the heart of our ASIC/SoC designs. RTL coding expertise isn’t a nice-to-have, it’s the core of this role.

Job Role,

Define and develop microarchitecture for high-performance AI SoC components.

Write clean, synthesizable RTL in Verilog/SystemVerilog with strong attention to detail.

Drive block-level design from concept to tape-out.

Work closely with architecture, DV, PD, and firmware teams to close design issues quickly.

Review specs, write design documentation, and contribute to design reviews.

Optimize for performance, power, and area without compromising functionality.

Debug issues during simulation, emulation, and silicon bring-up.

Expectation

7–15 years of experience in ASIC/SoC design.

Strong command over RTL coding — this is central to the role.

Hands-on experience in microarchitecture design.

Solid understanding of clocking, resets, FIFOs, arbiters, AXI/AMBA, coherency protocols, or datapath design.

Experience working with synthesis, lint, CDC, and power-intent flows.

Ability to break down complex problems and drive them to closure.

Exposure to AI accelerators, vector engines, or high-performance compute blocks is a bonus, not a barrier.

Cheers,

Shahid