🔹 Role: RTL Design Engineer

🔹 Experience: 3–8 years

🔹 Location: Bangalore (On-site)

🔹 Joining: Immediate to 15 Days

Key Requirements

• Strong hands-on expertise in Verilog

• Experience in SoC integration , especially with high-speed interfaces

• Good understanding of RTL design concepts and implementation

• Exposure to industry-standard design flows and tools

• PCIe protocol knowledge is an added advantage

What You’ll Work On

• RTL design and development for complex SoC components

• Integration of high-speed interfaces in advanced semiconductor designs

• Collaboration with verification and system teams

If you're looking to work on cutting-edge semiconductor projects in a fast-growing environment, this is a great opportunity.