We are currenly looking for a Processr Design Engineer .

• Focus areas include but are not limited to: Cache, Memory Management Unit (MMU), Multi-Core & Bus Coherence, Branch Prediction, Debug & Test Structures.
• Prospective team members require experience in at least one focus area; strong Verilog/SystemVerilog skills; RISC-V experience preferred.
• Master’s degree (or equivalent) and 2+ years of hands-on experience in a relevant role.
• Relocation required. Currently 4 days on-site, 1 day remote. Policy may change.
• Applicants with work-permits for Europe, i.e. Germany will be prioritized.

Ubitium is building a universal, workload-agnostic RISC-V microprocessor designed to reconfigure itself at runtime depending on what the application needs. Instead of stitching together specialized processors and toolchains, we’re creating a single unified compute platform.

At Ubitium, we believe the best engineering happens when people with different perspectives tackle hard problems together. We welcome applicants from all backgrounds and experiences. Our team members come from some of the best universities in the world and left some of the largest tech companies to build something truly remarkable.

We’re hiring people who want to build, not just maintain. You’ll get autonomy, high standards, and a team that moves quickly and supports each other. Bring depth, curiosity, and a bias for shipping.

We have multiple openings.

For more information visit: https://www.ubitium.com/career/