The verification Engineer position is your opportunity to join one of the industry’s leading companies in Smart Edge SoCs for network/systems control, management security systems, and IIoT.

You will be responsible for RTL SoC/Subsystem verification of ARM-based SoCs, and work on industry-standard verification methodologies like UVM, Portable Stimulus, and Formal verification flows. You will report to the Director of Engineering (Verification).

KEY RESPONSIBILITIES

• Help develop test plan definition
• Micro-architecture design verification, RTL verification, and documentation
• Top-level and block-level functional and performance verification, and system-level use-case verification; and
• Support test program development, chip validation, and chip life until production maturity.
• Team Management and Building
• Collaboration with firmware, software, DV, FPGA, DFT, SoC integration, and backend teams throughout various stages of ASIC development.

Qualifications

• 8-15 years of experience in UVM verification and UVM environment development (must have)
• Proficient in test plan definition and test case development in C/Assembly/System Verilog
• Expertise in verifying design at RTL level and gate-level simulation
• Good understanding of coverage analysis, performance verification, and use-case verification.
• Must have worked on AMBA AXI, AHB, and APB protocols
• Should have worked on verifying interface protocols like PCIe, USB, Ethernet, DDR3/4, LPDDR, I2C/I3C, SPI, SD/SDIO/eMMC, UART, etc.
• Experience in Jasper which is a formal verification platform from Cadence that helps with design verification at every stage of the design cycle
• Fluency with scripting languages (e.g., Perl, Python, Shell); and
• Experience in working with repository management tools like Bitbucket/ Jenkins and bug-tracking tools like JIRA.
• BE/BTECH or ME/MTECH degree in EE/EECS/CS or equivalent.

Contact

Sumit S. B

sumit@mulyatech.com

www.mulyatech.com

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