
EnCharge AI provides efficient, low‑power AI computing solutions that let businesses run advanced models from edge devices to the cloud. The company designs analog in‑memory computing chips and pairs…

EnCharge AI provides efficient, low‑power AI computing solutions that let businesses run advanced models from edge devices to the cloud. The company designs analog in‑memory computing chips and pairs…
Founded: 2022
Headquarters: Santa Clara, California
Tech focus: Analog in-memory AI accelerators and software for edge-to-cloud
Recent funding: Series B > $100M (announced Feb 2025)
Energy- and space-constrained AI inference acceleration for edge-to-cloud deployments.
2022
Data and Analytics
21700000
Emergence from stealth with $21.7M
22600000
Raised $22.6M to commercialize chips
100000000+
Series B announced as more than $100M
“Includes both financial and strategic investors such as Tiger Global, Samsung Ventures, CTBC/HH-CTBC, AlleyCorp, and others”
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www.EnchargeAi.com
Location : Bangalore
Principal Physical Design Engineer Floorplan & PDN
Bangalore
EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.
Experience: 14–20 Years
Location: Bangalore/2 days to work
Department: RTL-to-GDSII / Physical Implementation
Role Overview
We are seeking a high-caliber Principal Physical Design Engineer with a specialized mastery of Floorplanning and Power Delivery Network (PDN) design. You won’t just be pushing buttons; you will be the architectural bridge between RTL/Systems and the final GDSII. This role requires a visionary who understands how a single floorplan decision ripples through the entire PPA (Power, Performance, Area) spectrum.
As a technical lead, you will own the chip-top floorplan for complex, large-scale SoCs or Sub-chips, driving strategies that balance aggressive performance targets with robust power integrity.
Key Responsibilities
Technical Requirements
Behavioral Attributes
Education
Contact:
Uday
muday_bhaskar@yahoo.com
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