Principal Engineer DFT
Location:
Bengaluru, India
Experience:
12+ Years
Role Overview
We are seeking a
Principal Engineer DFT
who combines
strong hands-on DFT execution
with
architectural ownership
across complex IP and SoC designs. This role defines DFT strategy, drives implementation, and leads teams toward high-quality, testable silicon.
Key Responsibilities
DFT Architecture & Strategy
- Define and own
DFT architecture and test strategy
for IPs and full-chip SoCs.
- Architect
scan, compression, ATPG, MBIST
, and overall test infrastructure.
- Drive
early DFT engagement
to influence RTL, clocking, reset, and low-power architecture.
- Establish
DFT guidelines, best practices, and sign-off criteria
across programs.
- Evaluate trade-offs across
.
Hands-On Execution
- Lead and execute
scan insertion, ATPG pattern generation, and coverage closure
.
- Implement and debug
MBIST architectures
and memory test flows.
- Resolve complex
DFT issues
across RTL, synthesis, and post-layout stages.
- Work closely with
PD and STA teams
on test timing, constraints, and clocking.
- Support
post-silicon debug, yield analysis, and manufacturing bring-up
.
Technical Leadership & Collaboration
- Act as the
technical authority
for DFT across projects.
- Mentor and guide DFT engineers through reviews and hands-on support.
- Collaborate with
RTL, verification, physical design, and manufacturing teams
.
- Lead
DFT architecture reviews
and represent DFT in technical forums.
- Drive continuous improvement in
DFT methodology, automation, and reuse
.
Required Skills & Experience
- 12+ years
of experience in
DFT for IP and SoC designs
.
- Deep expertise in
DFT architecture, Scan, ATPG, and MBIST
.
- Strong hands-on experience with
industry-standard DFT tools
(Synopsys / Cadence / Siemens).
Why Join Us
- Architect DFT solutions for
next-generation silicon platforms
.
- High-impact role with
end-to-end ownership
.
- Work on large, complex
SoC designs
.
- Strong technical culture with growth toward
Fellow / Distinguished Engineer tracks
.
