Principal Digital Design Engineer | Powerlattice Inc · Teeming.ai
Powerlattice Inc
PowerLattice Technologies improves performance, efficiency, and reliability for AI accelerators and datacenter processors by bringing power closer to compute. It does this via power-delivery chiplets…
PowerLattice Technologies improves performance, efficiency, and reliability for AI accelerators and datacenter processors by bringing power closer to compute. It does this via power-delivery chiplets…
Your next opportunity is in here somewhere. Sign up to explore 52,000+ startups and their open roles. No spam. No gamification. Just jobs.
52,000+
Startups
65,000+
Open Roles
1,500+
New This Week
Technical Writer
InternshipNiš, RS
Internship • Niš, RS
DevOps Engineer
Part-timeCambridge, GB
Part-time • Cambridge, GB
Technical Writer
ContractBerlin, DE
Contract • Berlin, DE
Machine Learning Engineer
InternshipAmsterdam, NL
Internship • Amsterdam, NL
DevOps Engineer
InternshipNovi Sad, RS
Internship • Novi Sad, RS
Machine Learning Engineer
InternshipJerusalem
Internship • Jerusalem
Hybrid requiring 3 days a week onsite in the officeReports To: Head of EngineeringAbout Us
PowerLattice is a well-funded semiconductor start-up company backed by well-known large Silicon Valley VCs. The company is working on the industry’s groundbreaking chiplet solution for a fundamental shift in how high-performance chips get powered, paving the way for the next generation of AI and advanced computing.
About The Role
We are seeking a highly skilled and hands-on Principal Digital Design Engineer to drive the microarchitecture, design, and implementation of complex digital systems and SoC components. This role combines deep technical contribution with team leadership, requiring active involvement from microarchitecture definition through RTL development and into back-end implementation and silicon bring-up.
Key Responsibilities
Qualifications
This is a
Hybrid role requiring 3 days a week onsite at our HQ’s in Vancouver, WA (Greater Portland Area) or Chandler, AZ.While we are primarily seeking candidates in HQ-Vancouer and Chandler, remote flexibility may be considered for exceptional candidates in Silicon Valley, CA.
Preferred Qualifications
Familiarity with advanced technology nodes and implementation challenges
Experience with formal verification techniques
Experience with silicon bring-up and post-silicon debug
Compensation & Benefits
Competitive salary
Stock option grant
Comprehensive benefits package including health, dental, vision, and 401(k)
Architecture & Hands-On Design
Define microarchitecture for complex digital blocks and subsystems
Actively contribute to RTL development for key components
Drive design tradeoffs across performance, power, area (PPA), and testability
RTL Development & Integration
Write, review, and integrate high-quality RTL
Lead block- and chip-level integration, resolving interface and system issues
Ensure designs are clean for lint, CDC/RDC, and synthesis
Back-End & Implementation Ownership
Ensure RTL is optimized for synthesis, timing, and physical design
Work on scan insertion, test architecture, and coverage closure
Perform, review and debug logic equivalence checking (LEC) results between RTL and netlists
Define and validate timing constraints (SDC) and complete timing closure
Drive and implement timing and functional ECOs as needed
Design Quality & Signoff
Drive signoff readiness including lint, CDC/RDC, synthesis, LEC, and timing checks
Ensure designs meet functional, timing, power, and test requirements
Support silicon bring-up, debug, and root-cause analysis
Cross-Functional Collaboration
Work closely with verification, physical design, DFT, and firmware teams
Align design decisions with verification plans and implementation Constraints
Act as the technical bridge between front-end and back-end teams
Bachelor's or master's degree in electrical engineering, Computer Engineering, or related field
10+ years of experience in digital design with significant hands-on RTL development
Proven track record of delivering complex SoC or subsystem designs to tapeout
Strong expertise in:
RTL design and microarchitecture
SoC integration and standard interfaces
Hands-on experience with back-end flows, including:
Scan insertion and DFT (scan, MBIST, test coverage)
Logic equivalence checking (LEC)
Static timing analysis (STA) and timing closure
Timing constraint development and debug (SDC)
Solid understanding of:
Clocking, resets, CDC/RDC, and low-power design
Synthesis and physical design implications
Experience with industry-standard EDA tools (Synopsys, Cadence)
