Senior Digital/RTL IC Design Engineer

Bangalore

Engineering – Digital Circuit Design /

Full-time /

Principal Digital Design Engineer focusing on the digital datapath of high-performance analog-to-digital and digital-to-analog converters. Job responsibilities include RTL design, verification, behavioral modelling, support and assist with synthesis, timing closure and P&R flow for the digital controller for high performance data converters in cutting edge technologies

Qualifications

• BS/BE/MS/MTech + 8-12 years or equivalent experience in high-performance digital or mixed-signal IC development in advanced CMOS processes
• Strong foundation in digital design concepts for complex ASICs
• Hands on experience with the Verilog RTL coding including state machines, adders, multipliers, combinatorial logic, etc
• Strong understanding of digital design for mixed signal control loops and designing Verilog code to control analog circuits (e.g. digital backend for ADC, digital PLL, etc)
• Familiarity with behavioral Verilog code, including wreals
• Ability to write thorough testbenches
• Preferred knowledge of Genus, Tempus, Modus and other Cadence tool set used for ASIC design flow
• Excellent understanding of SystemVerilog
• Knowledge of SystemVerilog assertions preferred

Contact:

Uday

Mulya Technologies

muday_bhaskar@yahoo.com

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