Design Verification Engineer : PCIE/CXL Focused

Job Description

In this role you will be working on high performance server class PCIe/CXL controllers and multi-controller sub-systems at block and SoC level. The task list includes, but is not limited to, testplan development, env development, checker/scoreboard development, test execution and analysis at sub-system, chiplet and multi-chiplet level

Roles And Responsibilities

• Partner with Architects and RTL Design team to grasp high-level system requirements and specifications.
• Formulate comprehensive test and coverage plans to match the Architecture and micro-architecture.
• Develop the verification environment and reusable bus functional models, stimulus, checkers, assertions, trackers, and coverage metrics.
• Create verification plans and develop testbenches tailored to assigned IP/Sub-system or functional domain.
• Execute verification plans, including tasks such as design bring-up, setting up the DV environment, running regressions for feature validation, and debugging test failures.
• Support post-Si bring-up and debug activities.
• Track and communicate progress in the DV process by using key metrics like testplan status, bug tracking and coverage reports.

Requirements

• Bachelor’s or Master’s degree in Electrical/Electronics Engineering/Science with 10 to 18 years of relevant experience
• Strong Architecture domain knowledge in latest generation of PCIE and CXL protocols, PIPE, serdes.
• Must have strong expertise with SV/UVM methodology and/or C/C++ based verification with 5yrs+ hands-on experience in IP/sub-system and/or SoC level verification
• Hands on experience and expertise with industry standard verification tools for simulation and debug (Questa/VCS, Visualizer)
• Experience using random stimulus along with functional coverage and assertion-based verification methodologies a must.

Preferred Qualifications:

• Experience in development of UVM based verification environments from scratch.
• Hands on expertise with PCIE/CXL controller and sub-system verification as root/host and end-point/client
• Hands on expertise and protocol knowledge in any of: APB/AXI protocols , PCIE/CXL protocols and compliance testing
• A strong drive for DV infrastructure automation

Contact:

Uday

Mulya Technologies

muday_bhaskar@yahoo.com

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