Principal Design Verification Engineer: DDR Focused

Job Description

In this role you will be working on Memory Sub-system block for an advanced high performance server class AI and compute design. The task list includes, but is not limited to, testplan development, env development, checker/scoreboard development, test execution and analysis at sub-system, chiplet and multi-chiplet level

Roles And Responsibilities

• Partner with Architects and RTL Design team to grasp high-level system requirements and specifications.
• Formulate comprehensive test and coverage plans to match the Architecture and micro-architecture.
• Develop the verification environment and reusable bus functional models, stimulus, checkers, assertions, trackers, and coverage metrics.
• Create verification plans and develop testbenches tailored to assigned IP/Sub-system or functional domain.
• Execute verification plans, including tasks such as design bring-up, setting up the DV environment, running regressions for feature validation, and debugging test failures.
• Support post-Si bring-up and debug activities.
• Track and communicate progress in the DV process by using key metrics like testplan status, bug tracking and coverage reports.

Requirements

• Bachelor’s or Master’s degree in Electrical/Electronics Engineering/Science with 10 to 18 years of relevant experience
• Strong Architecture domain knowledge in LPDDR5 (controller and PHY), HBM, DDR5 and allied technologies and memory sub-systems
• Must have strong expertise with SV/UVM methodology and/or C/C++ based verification with 5yrs+ hands-on experience in IP/sub-system and/or SoC level verification
• Hands on experience and expertise with industry standard verification tools for simulation and debug (Questa/VCS, Visualizer)
• Experience using random stimulus along with functional coverage and assertion-based verification methodologies a must.

Preferred Qualifications:

• Experience in development of UVM based verification environments from scratch.
• Hands on expertise and protocol knowledge DDR protocols, memory controllers, DDR compliance testing
• Hands on expertise and protocol knowledge in any of: APB/AXI protocols, I2C/I3C
• A strong drive for DV infrastructure automation

Contact:

Uday

Mulya Technologies

muday_bhaskar@yahoo.com

"Mining The Knowledge Community"