At d-Matrix , we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration. We value humility and believe in direct communication. Our team is inclusive , and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together , we can help shape the endless possibilities of AI.

Location: Hybrid, working onsite at our Santa Clara, CA, headquarters 3-5 days per week.

Job Description We are looking for a Principal ATE Test Engineer with proven experience in developing and supporting complex silicon SoC products to lead ATE test solutions. The ideal candidate will develop and oversee SoC test strategy, interact with manufacturing partners, define and implement ATE programs, and own the product from design and initial samples all the way through high volume production ramp. The candidate should have working knowledge of CPU and communication/interface protocols such as PCI-Express (Gen-4/5/6), High Speed D2D, LPDDR (4/5/6), etc. The candidate will also need to work with OSAT to identify and drive test cost reduction, improve both CP and FT yield, identify FT high yield fallout bins, and enhance CP program to minimize such high FT yield fallout bins.

Basic Qualifications

• Strong academic and technical background in electrical engineering. At minimum, a bachelor’s in EE is required, and a master’s is preferred
• 12 + years of experience developing & releasing complex SoC/silicon products to high volume manufacturing
• Experience with developing high pin count wafer sort probe cards and load boards
• Has implemented Scan, at speed Scan, MBist, Serdes loopback
• Working knowledge of high-speed protocols like PCIe, LPDDRx, HBM, etc.
• Professional attitude with the ability to execute multiple tasks with minimal supervision
• Strong team player with good communication skills to work alongside a team of high caliber engineers

Required Experience

• Hands-on experience with high-speed SoC test program/hardware development on the Advantest 93k test platform

Preferred Experience

• Fluent in data processing using high level programming languages
• Experience in running internal loopback at wafer sort as well as at FT
• Familiarity with database setup using JMP as YMS (Yield Management Tool)

Equal Opportunity Employment Policy d-Matrix is proud to be an equal opportunity workplace and affirmative action employer. We’re committed to fostering an inclusive environment where everyone feels welcomed and empowered to do their best work. We hire the best talent for our teams, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. Our focus is on hiring teammates with humble expertise, kindness, dedication and a willingness to embrace challenges and learn together every day.

d-Matrix does not accept resumes or candidate submissions from external agencies. We appreciate the interest and effort of recruitment firms, but we kindly request that individual interested in opportunities with d-Matrix apply directly through our official channels. This approach allows us to streamline our hiring processes and maintain a consistent and fair evaluation of al applicants. Thank you for your understanding and cooperation.